An efficient scheduler of RTOS for multi/many-core system

Gu, Xiongli; Liu, Peng; Yang, Mei; Yang, Jie; Li, Cheng; Yao, Qingdong

doi:10.1016/j.compeleceng.2011.09.009

Cited by 7 publications

(6 citation statements)

References 27 publications

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“…We also plan to study the possibility of extending USG to supercomputing and cloud computing, as has been presented in [29,30].…”

Section: Resultsmentioning

confidence: 98%

“…LLF fails to schedule the above-mentioned example because task T 3 can only take the processor in the intervals [9,10], [19,20], and [29,30] before it can be prioritized over T 1 and T 2 at time t = 36, when it will have zero laxity. Therefore, T 3 will be executed to completion before its deadline at time t = 40.…”

Section: Examplementioning

confidence: 93%

“…In line 28, the task Id of the processor is updated to the Id of the zero laxity task (Tw). Now, both tasks are ready to be replaced, and thus, task (Tw) is added to heap H R , while task (Tr) is added to heap H W (lines [29][30]. The while loop in line 21 then continues until all Z events are handled.…”

Section: The Handleeorzevents Proceduresmentioning

confidence: 98%

See 2 more Smart Citations

An unfair semi-greedy real-time multiprocessor scheduling algorithm

Alhussian

Zakaria

Patel

2016

Computers & Electrical Engineering

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“…We also plan to study the possibility of extending USG to supercomputing and cloud computing, as has been presented in [29,30].…”

Section: Resultsmentioning

confidence: 98%

Section: Examplementioning

confidence: 93%

See 1 more Smart Citation

An unfair semi-greedy real-time multiprocessor scheduling algorithm

Alhussian

Zakaria

Patel

2016

Computers & Electrical Engineering

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“…It does not support manual task switching through any system calls. It will considerably increase the overhead by changing work-item task priority or through synchronization module such as semaphore [8] to allow expected execution sequence. Task schedule overhead is heavy when using DSP/BIOS kernel, and it involves task stack change and context switch.…”

Section: Second Level Rtos Schedulermentioning

confidence: 99%

“…It is a challenging task to support OpenCL program model on multicore DSP for embedded application. We address this problem by firstly utilizing the LLVM (low level virtual machine) [5] and Clang [6] open source compiler to support kernel compilation and further optimization for the DSP platform; then we designed 2 Advances in Mechanical Engineering [7,8] scheduler that aimed to schedule work-item in a work group to decrease the task switching overhead. Finally, we proposed a kind of software managed CACHE method to efficiently administrate the distributed global memory which was combined through interconnections such as PCIE, SRIO (serial rapid IO), Hyperlink, and SGMII.…”

Section: Introductionmentioning

confidence: 99%

A Two-Level Task Scheduler on Multiple DSP System for OpenCL

Tian

Cai

Zhou

2014

Advances in Mechanical Engineering

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This paper addresses the problem that multiple DSP system does not support OpenCL programming. With the compiler, runtime, and the kernel scheduler proposed, an OpenCL application becomes portable not only between multiple CPU and GPU, but also between embedded multiple DSP systems. Firstly, the LLVM compiler was imported for source-to-source translation in which the translated source was supported by CCS. Secondly, two-level schedulers were proposed to support efficient OpenCL kernel execution. The DSP/BIOS is used to schedule system level tasks such as interrupts and drivers; however, the synchronization mechanism resulted in heavy overhead during task switching. So we designed an efficient second level scheduler especially for OpenCL kernel work-item scheduling. The context switch process utilizes the 8 functional units and cross path links which was superior to DSP/BIOS in the aspect of task switching. Finally, dynamic loading and software managed CACHE were redesigned for OpenCL running on multiple DSP system. We evaluated the performance using some common OpenCL kernels from NVIDIA, AMD, NAS, and Parboil benchmarks. Experimental results show that the DSP OpenCL can efficiently exploit the computing resource of multiple cores.

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The multi-core parallel algorithms of wavelet/wavelet packet transforms and their applications in power system harmonic analysis and data compression

Liu

Geng

Xie

et al. 2014

Int. Trans. Electr. Energ. Syst.

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SUMMARYThe multi-core technology can not only provide the computation in parallel but also avoid the redundancy costs by the communication and maintenance of multi-machine network structure. This paper uses the multi-core technology to achieve the parallelism of wavelet and wavelet packet transforms, so that the computation speed is increasing and the time is shortening in the practical applications. The parallel algorithms of wavelet and wavelet packet transforms, respectively, on the basis of POSIX thread and OpenMP are proposed and realized. The parallel results can meet the requirements by comparing parallel algorithms with the serial algorithms of single-layer and multi-layer transforms. For OpenMP, the paper takes the guidance statements to parallelize the loops of serial programs. In addition, the paper proposes one kind of nesting and non-nesting parallel means of wavelet packet transform and compares the parallel results with the serial programs. The experimental results show that the speedup is increasing with the amount of data and finally closing to 2. It is shown that the proposed parallel algorithms can improve the transform speed significantly. These parallel algorithms are applied in the harmonic analysis and data compression of power system, and a parallel strategy for compression with bitmap is proposed. The results show that the parallel algorithms of wavelet and wavelet packet transforms can improve the analysis and compression speed significantly.

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An efficient scheduler of RTOS for multi/many-core system

Cited by 7 publications

References 27 publications

An unfair semi-greedy real-time multiprocessor scheduling algorithm

An unfair semi-greedy real-time multiprocessor scheduling algorithm

A Two-Level Task Scheduler on Multiple DSP System for OpenCL

The multi-core parallel algorithms of wavelet/wavelet packet transforms and their applications in power system harmonic analysis and data compression

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