An efficient layout style for 2-metal CMOS leaf cells and their automatic generation

Hwang, Chi-Yi; Hsieh, Yung-Ching; Lin, Youn-Long; Hsu, Yu-Chin

doi:10.1145/127601.127716

Cited by 9 publications

(3 citation statements)

References 20 publications

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“…For X1, X2, and X4, which have large pattern areas, we can approximate that these values are directly proportional. We further investigated the relationship between the channel width and number of cells in relation to three types of cell libraries [9,13,14]. Figures 16(a), (b), and (c) show those results.…”

Section: Prediction Of Pattern Area Reduction Effect From Cell Librarymentioning

confidence: 96%

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Design methodology for system LSI with TIS (trench-isolated transistor using sidewall gate)

Watanabe

2006

Electron. Comm. Jpn. Pt. II

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SUMMARYThe author proposes a design methodology that uses TIS for a system LSI chip that consists primarily of NAND and NOR gate logic. They use a system LSI chip for communication as an example to show that the planar + TIS architecture is effective in reducing the pattern area in a system LSI chip that is designed by using a cell library. The planar + TIS architecture uses the TIS architecture for parts in which the transistor channel width is large and the planar architecture for parts in which it is small. When the minimum channel width of a transistor is set to 5F (F is the minimum line width), the pattern area consisting of the element area and element isolation area can be reduced to 25% to 36% of the area for the planar architecture by setting the trench depth to D = 2F or 4.5F.

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Section: Prediction Of Pattern Area Reduction Effect From Cell Librarymentioning

confidence: 96%

“…13 occupies 90% of the total area and the X2 + X3 pattern area occupies 9%, while in the consumer-oriented ASIC chip in Ref. 9, the X1 pattern area occupies 88% and the X2 + X3 pattern area occupies 12%. In both of these cases, most of the area is occupied by X1.…”

Section: Prediction Of Pattern Area Reduction Effect From Cell Librarymentioning

confidence: 99%

Design methodology for system LSI with TIS (trench-isolated transistor using sidewall gate)

Watanabe

2006

Electron. Comm. Jpn. Pt. II

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“…Furthermore, research focuses on new layout styles for cell and module generation, e.g. [Ka87] [Hw91].…”

Section: Introductionmentioning

confidence: 99%

Complex gate performance improvement by jog insertion into transistor gates

Hindmarsh

Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93

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This paper describes how the insertion of 45 degree jogs into transistor gates leads to performance improvement of static CMOS complex gates. Therefore, CMOS complex gates were designed using a new layout style called Jogged Gate Matrix Layout (JOGM). SPICE3 simulation results exhibit an up to 44% speed improvement in comparison to traditional gate matrix layout style, due to reduced diffusion capacitances. JOGM also improves cell width by up to 31%.

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