An efficient interpolation filter VLSI architecture for HEVC standard

Abstract

The emerging video coding standard, High Efficient Video Coding (HEVC), aims at doubling coding efficiency of H.264/AVC. Fractional Motion Estimation (FME) in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40% of the total encoding time and its high computational complexity. Firstly, this paper proposes a fast interpolation filter algorithm, which is based on the 8-pixel interpolation unit. It can save 9.9% processing time on average while introducing only 0.1256% BD_PSNR coding quality degradation. Based on this, the paper designs and realizes the interpolation filter VLSI architecture with the reconfigurable configuration and the cell block reuse to reduce the implement hardware area. The final VLSI implementation only requires 64.5k gates in a standard 90nm CMOS technology at an operating frequency of 193MHz. The proposed architecture can be reused for halfpixel interpolation and quarter-pixel interpolation, which can reduce the area cost for about 131040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 3840×2160@47fps video sequences.

An efficient interpolation filter VLSI architecture for HEVC standard

“…In this paper, we extend our earlier work [18] in three ways. First, on the basic of our original algorithm, we skip the 4 × 8, 4 × 16, 8 × 4, 16 × 4, 16 × 12, and 12 × 16 sub-PU blocks in the interpolation process instead of only skipping the 4 × 8, 4 × 16, and 12 × 16 PU, to further save the encoding time and save a large area in hardware implementation by skipping 4× size with acceptable coding quality degradation.…”

“…A PC with Inter Core™i5-2400K CPU @ 3.1GHz and 4-G RAM is used in the experiments. We compare the proposed algorithm and our previous work [18] in a low complexity configuration with the original algorithm in HM 13.0 encoder. The performance of the proposed algorithm is shown in Table 4.…”

“…Another obvious limitation of our earlier work [18] and the above progress is that they only target at the video applications with the resolutions up to HD or 4K. For higher throughput of 8K-UHD 7680 × 4320, more efficient hardware architecture is desirable.…”

“…To overcome the obstacles of the previous work, we proposed a fast interpolation filter algorithm and the corresponding hardware architecture in [18], which can save the encoding time and reduce the computational complexity of fractional motion estimation in HEVC. In the aspect of algorithm, we speed up the encoding process by skipping all the 4 × 8, 4 × 16, and 12 × 16 prediction units in the queue.…”

“…There have been many previous works focusing on designing efficient architecture for HEVC MC interpolations [11][12][13][14][15][16][17][18]. Huang proposed a high-throughput interpolation filter architecture with a prediction unit (PU)-adaptive filtering flow and a unified filter combining the eight-tap luma and four-tap chroma filters [11].…”