Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture

Diniz, Cláudio M.; Fonseca, Mateus Beck; Costa, Eduardo; Bampi, Sérgio

doi:10.1007/s10470-016-0765-6

Cited by 6 publications

(4 citation statements)

References 13 publications

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“…apath, by relying on the symmetries of the HEVC interpolation filters. This work was extended to reduce power of HEVC interpolation by employing dynamic reconfigurability in field-programmable gate arrays [12], and adder compressors [13]. The works [11][12][13] provide precise solutions that do not affect BD-Rate.…”

Section: Related Workmentioning

confidence: 99%

“…This work was extended to reduce power of HEVC interpolation by employing dynamic reconfigurability in field-programmable gate arrays [12], and adder compressors [13]. The works [11][12][13] provide precise solutions that do not affect BD-Rate. Afonso et al [14] propose a hardware architecture for FME in HEVC, thus including a interpolation unit and comparison units for the search phase.…”

Section: Related Workmentioning

confidence: 99%

“…All those works [11][12][13][14][15][16]18] target HEVC interpolation filtering, which is 17× less complex than VVC interpolation filtering, as we motivated in the introduction. Performance, power, and energy of HEVC and VVC interpolation filters cannot be directly compared.…”

Section: Filters Coefficientsmentioning

confidence: 99%

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Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Silva

Siqueira

Grellert

et al. 2021

JICS

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The new Versatile Video Coding (VVC) standard was recently developed to improve compression efficiency of previous video coding standards and to support new applications. This was achieved at the cost of an increase in the computational complexity of the encoder algorithms, which leads to the need to develop hardware accelerators and to apply approximate computing techniques to achieve the performance and power dissipation required for systems that encode video. This work proposes the implementation of an approximate hardware architecture for interpolation filters defined in the VVC standard targeting real-time processing of high resolution videos. The architecture is able to process up to 2560x1600 pixels videos at 30 fps with power dissipation of 23.9 mW when operating at a frequency of 522 MHz, with an average compression efficiency degradation of only 0.41% compared to default VVC video encoder software configuration.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Silva

Siqueira

Grellert

et al. 2021

JICS

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“…For this task, employing adder compressors (ACs) is a promising alternative for low-power designs. ACs parallelization schemes allow the reduction of the hardware architecture's internal switching activity, which proportionally reduces the dynamic power dissipation, compared with the combination of the conventional carry propagating adders [15,16].…”

Section: Introductionmentioning

confidence: 99%

Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

Ferreira

Paim

Rocha

et al. 2021

IET Computers & Digital Tech

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Fast Fourier transform (FFT) is the most common low‐complexity implementation of the discrete Fourier transform, intensively employed to process real‐world signals in smart sensors for the internet of things. Butterflies play a central role as the FFT computing core data path since it calculates complex terms employing several multipliers. A low‐power FFT hardware architecture combining split‐radix decimation‐in‐time butterfly and 5‐2 adder compressors (ACs) is proposed and implemented. The circuits are described in Verilog hardware description language and synthesized using the Cadence Genus synthesis tool. The circuits are mapped onto a 65‐nm CMOS ST standard cell library. Results reveal that the proposed FFT hardware architecture using the split‐radix butterfly is 13.28% more power efficient than the radix‐4 one. The results further show that, by combining 5‐2 AC within the split‐radix butterfly, our proposal saves up to 43.1% of the total power dissipation considering the whole FFT hardware architecture, compared with the state‐of‐the‐art radix‐4 butterfly employing the adder automatically selected by the logic synthesis tool.

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The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

Silveira

Paim

Abreu

et al. 2021

Circuits Syst Signal Process

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Evaluating the use of adder compressors for power-efficient HEVC interpolation filter architecture

Cited by 6 publications

References 13 publications

Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Approximate Hardware Architecture for Interpolation Filter of Versatile Video Coding

Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

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