An efficient implementation of the 1D DCT using FPGA technology

El-Banna, H. H.; El-Fattah, A.A.; Fakhr, W.

doi:10.1109/ecbs.2004.1316719

Cited by 12 publications

(7 citation statements)

References 13 publications

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“…1D DCT blocks along row and column implement 2D DCT. In the proposed architecture of 1D Fast Discrete Cosine Transform, it has been implemented by Distributed Arithmetic [16], [19] in Fig. 8.…”

Section: Fast Fourier Transformmentioning

confidence: 99%

A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays

Sinha

Sarkar

Acharyya

et al. 2013

SIGARCH Comput. Archit. News

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Development of modern integrated circuit technologies makes it feasible to develop cheaper, faster and smaller special purpose signal processing function circuits. Digital Signal processing functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or lower speed compared to ASIC. Field Programmable DSP Array (FPDA) is the proposed DSP dedicated device, redolent to FPGA, but with basic fixed common modules (CMs) (like adders, subtractors, multipliers, scaling units, shifters) instead of CLBs. This paper introduces the development of reconfigurable system architecture with a focus on FPDA that integrates different DSP functions like DFT, FFT, DCT, FIR, IIR, and DWT etc. The switching between DSP functions is occurred by reconfiguring the interconnection between CMs. Validation of the proposed architecture has been achieved on Virtex5 FPGA. The architecture provides sufficient amount of flexibility, parallelism and scalability.

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Section: Fast Fourier Transformmentioning

confidence: 99%

A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays

Sinha

Sarkar

Acharyya

et al. 2013

SIGARCH Comput. Archit. News

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“…The discrete Cosine Transform is defined as a matrix multiplication which is illustrated below [7][8].…”

Section: Fast Cosine Transform Based On Direct Algorithmmentioning

confidence: 99%

“…A number of architectures are proposed for the realization of these transforms [2][3][4][5][6][7]. However, a unified architecture, which can compute all these transforms, can serve the purpose of a general DSP chip, and therefore a unified architecture has been adopted to obtain all the transforms in a single FPGA chip.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Semi-Unified High Performance Signal Processing Coprocessor

Mahdavi¹,

Amiri²

2012

AJSP

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Utilizing the DFT, the DHT, the DCT or the DST is an obvious choice in signal processing domain. This paper describes the implementation of a semi-unified high performance coprocessor of transform length '8' for the synchronous design in XC3S1400AN-4FG484 FPGA device of Xilinx Company. The operating frequency of 20 MHz is achieved. The paper presents the trade-offs involved in designing the architecture, the design for performance issues and the possibilities for future development.

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“…The high capability and performance that FPGAs have achieved in recent years allow them to accelerate DSP tasks. FPGA devices have been used to implement Custom DSPs since the beginning of this decade [2]. Usually, FPGAs are used as VLSI replacement on low volume production or prototyping devices which are to be eventually implemented as ASICs [1].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a 118 MHz 2D DCT processor

Atani

Baboli

Mirzakuchaki

et al. 2008

2008 IEEE International Symposium on Industrial Electronics

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Frequency analysis using the Discrete Cosine Transforms (DCT) is an obvious choice for Digital signal and Image processing domain. This paper describes the implementation of 2D-DCT processor for the synchronous design in a Xilinx VertexIV FPGA device. The DCT core architecture is based on the distributed arithmetic. The total dynamic power of the processor is 371 mW, in an operating frequency of 118.2 MHz is achieved. The paper presents the trade-offs involved in designing the architecture, the design for performance issues and the possibilities for future development.

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An efficient implementation of the 1D DCT using FPGA technology

Cited by 12 publications

References 13 publications

A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays

A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays

Design and Implementation of a Semi-Unified High Performance Signal Processing Coprocessor

Design and implementation of a 118 MHz 2D DCT processor

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