Design and implementation of a 118 MHz 2D DCT processor

Abstract

Frequency analysis using the Discrete Cosine Transforms (DCT) is an obvious choice for Digital signal and Image processing domain. This paper describes the implementation of 2D-DCT processor for the synchronous design in a Xilinx VertexIV FPGA device. The DCT core architecture is based on the distributed arithmetic. The total dynamic power of the processor is 371 mW, in an operating frequency of 118.2 MHz is achieved. The paper presents the trade-offs involved in designing the architecture, the design for performance issues and the possibilities for future development.

An efficient low area implementation of 2-D DCT on FPGA

“…Their main difference is due to their implementations of 1-D DCT core, which will also be evident in the following tables. According to Table 1, the proposed design and [6] result in similar device utilizations except for DSP48 and Block RAM resources. The design in [6] does not use any multiplier and relies heavily on Block RAMs for the implementation of a 2-D DCT architecture based on distributed arithmetic.…”

“…The proposed 2-D DCT architecture is compared against two other competitive designs implemented for Virtex IV and Spartan 3E by [6] and [8] in Table 1 and Table 2, respectively. It should be noted here that both [6] and [8] are based on the rowcolumn decomposition method and use two 1-D DCT cores with a transpose buffer between them.…”

“…It should be noted here that both [6] and [8] are based on the rowcolumn decomposition method and use two 1-D DCT cores with a transpose buffer between them. Their main difference is due to their implementations of 1-D DCT core, which will also be evident in the following tables.…”

“…2, w[39:0] denotes the set of weights used during a multiplication. For example, z 2 = b * ×X 0 + f * ×X 2 f * ×X 4 b * ×X 6 and w[39:0] ={b * , f * , -f * , -b * }, where * is used to indicate 10-bit 2's complement representations of the related weight values. Even though it is not shown in Fig.…”

“…Among the various architectures and algorithms proposed for the computation of 2-D DCT, a popular approach is the rowcolumn decomposition method [4][5][6][7][8][9][10]. Its popularity can be attributed to the following facts: (i) It is based on the separability property of 2-D DCT and enables the computation of 2-D DCT by using two successive 1-D DCT transforms.…”