An efficient high speed squaring and multiplier architecture using yavadunam sutra and bit reduction technique

Deepa, A.; Marimuthu, C. N.; Murugesan, C

doi:10.1088/1742-6596/1432/1/012080

Cited by 9 publications

(8 citation statements)

References 2 publications

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“…Squaring is an exclusive case of multiplication [11,12]. Yavadunam sutra has been used to square a number; it means that, ''determine deficiency, lessen the deficiency from that number and write the square of the deficiency'' [10][11][12]21]. Yavadunam Tavadunikrtya Vargancha Yojayet (YTVY) is up-sutra of the sutra Yavadunam.…”

Section: Vedic Squaring -Yavadunammentioning

confidence: 99%

“…The principles of Yavadunam sutra is implemented to obtain the deficiency from the nearest base value. The following are the steps to be pursued to multiply two numbers using Yavadunam sutra [11,12]. Let A and B be the two numbers to be multiplied.…”

Section: As Per the Previous Sectionmentioning

confidence: 99%

“…Yavadunam sutra does not possess any hardware or architecture till now. This made us to work on this squaring sutra and design architecture for the existing sutra [11,12]. Here the deficiencies are obtained by using the principles of Yavadunam sutra *For correspondence and the same have been implemented and high speed binary multiplier is designed.…”

Section: Introductionmentioning

confidence: 99%

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Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Deepa¹,

Marimuthu²

2019

Sādhanā

Self Cite

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In current day situation we come across numerous mathematical challenges. This could be overwhelmed by the Vedic Mathematics. Vedic Mathematics is an ancient approach to solve problems in a rapid manner. In this paper the design of a novel Vedic square and multiplier architecture based on Yavadunam Sutra is proposed. Yavadunam is a squaring sutra of the Vedic Mathematics. We have designed a generic architecture for this squaring sutra and have designed a high speed Vedic binary multiplier architecture using the principles of Yavadunam sutra. The proposed multiplier offers significant improvement in speed. Xilinx Spartan FPGA is used to design and realize the architecture and the Synopsys device with 90 nm and 180 nm technology is used to synthesize the same.

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Section: Vedic Squaring -Yavadunammentioning

confidence: 99%

Section: As Per the Previous Sectionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Deepa¹,

Marimuthu²

2019

Sādhanā

Self Cite

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“…The drastic growth in digital technology and the expansion of digital signal processing (DSP) applications increase the demand for high-speed processing, which is possible by the high throughput arithmetic operations [1]. Arithmetic Logic Units (ALUs) are the vital blocks of processors that perform various arithmetic operations such as addition, subtraction, division, multiplication, and squaring [2].…”

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture

Varnosfaderani

Rashidi

Alhawari

2022

COMPUTE

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This paper presents the design of a high speed and simple squaring structure based on half adder and full adder. The proposed architecture consists of three main steps; simplification of the squaring structure, calculation and transferring of the carry bit to the next part, and finally, applying the modified Wallace Tree Adder to calculate the summation of the products. The proposed squaring architecture is formed only by 13 half adders and 20 full adders for 8-bit squaring which has the lowest complexity compared to other works. The proposed structure is modeled by using Field-Programmable Gate Array (FPGA) and has been successfully synthesized and implemented with Xilinx Spartan-6 and Virtex-4 FPGA. Simulation results show that the proposed structure has high speed and excellent performance with low power consumption while having the lowest propagation delay (3.25 ns) and acceptable hardware utilization compared to existing squaring models. The gate-level design of 8-bit squaring is implemented using Cadence layout tools in 65 nm CMOS technology which has a total area of 0.095 mm2.

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“…P. Ramanammma [15] has created low-power architectures with less area and delay for squaring and cubing the numbers utilizing the Duplex property of Vedic mathematics to be employed in arithmetic/ logic units. After that, A. Deepa et al [16] used the Yavadunam algorithm and a technique to reduce the bits for developing a Vedic squaring team to improve the speed, area, and power consumption of the squaring unit. To further enhance the speed and location, authors in [17] had developed a squaring circuit for a 2-bit number using Nikhilam Sutra rules to accomplish an 8-bit squarer using the repetitive procedure.…”

Section: Introductionmentioning

confidence: 99%

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

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Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24-bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12-bit, and 24-bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24-bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

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An efficient high speed squaring and multiplier architecture using yavadunam sutra and bit reduction technique

Cited by 9 publications

References 2 publications

Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture

Vedic-Based Squarers with High Performance

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