An efficient hardware model for RSA Encryption system using Vedic mathematics

Bhaskar, R.; Hegde, Ganapathi; Vaya, P. R.

doi:10.1016/j.proeng.2012.01.842

Cited by 21 publications

(9 citation statements)

References 1 publication

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“…The Comparison between proposed Vedic divider and restoring divider is shown in table (1). As from the table this divider helps in future to make fast processors.…”

Section: Resultsmentioning

confidence: 96%

Implementation of vedic divider on RSA cryptosystem

Subudhi

Karthick

2015

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

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RSA cryptosystem is an old and premier public key cryptography, which is used for data security. A divider is one of the key hardware blocks in most applications such as digital signal processing, cryptography and in other logical computations. Low power consumption, high speed and smaller area are some of the most important aspects for designing of any VLSI system. Area and speed are usually incompatible constraints. So good design has to set equilibrium between area and speed. It is also known fact that Divider unit forms an integral part of processor design. Due to this regard, high speed divider architecture becomes the need of the day. This paper deals with the implementation of vedic divider in RSA algorithm instead of conventional divider. Vedic mathematics describes a method called 'Dhvajanka -On the top of flag' which is a generalized formula for Vedic division used in vedic divider. Veri log code is programmed and simulated by Quartus II 9.0 . Power dissipation has been reduced. Significant improvement has been observed in terms of area utilization and time delay.

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“…The Comparison between proposed Vedic divider and restoring divider is shown in table (1). As from the table this divider helps in future to make fast processors.…”

Section: Resultsmentioning

confidence: 96%

Implementation of vedic divider on RSA cryptosystem

Subudhi

Karthick

2015

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

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“…The author of [14] has stated that for providing security to information cryptography involves privacy, confidentiality, key exchange, authentication, and non-repudiation. The author of [15] has stated that RSA is standard algorithm that use Public-key, Private-key for providing security to data in networks.…”

Section: Review Of Literaturementioning

confidence: 99%

Integration of Cryptography Standards and Steganography for Secure Communication

Gavde¹,

Darekar²,

Sharma³

2018

IJCA

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Securing the massive amount of data is one of the greatest challenges and it is equally important to ensure data privacy. When the data transmitted from one computer to another, the probability of accessing the data by unauthorized user becomes high. This paper proposes a solution to enhance the security of data, using both cryptography and steganography. The key focus of this paper is to provide confidentiality of data and authentication of user.

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“…Shift operation is not necessary because the partial product calculation will perform it in a single step, which in turn saves time and power. This is the main advantage of the Vedic multiplier [14].…”

Section: B Urdhava Triyagbhayam Sutramentioning

confidence: 99%

A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate

Anitha

Deshmukh

Agarwal

et al. 2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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The Vedic Multiplier and the Reversible LogicGates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area .The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Modelsim, Xilinx 14.2 and synthesis is done in both RTL compiler using cadence as well as Xilinx. The chip design for the proposed MAC is also carried out.

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An efficient hardware model for RSA Encryption system using Vedic mathematics

Cited by 21 publications

References 1 publication

Implementation of vedic divider on RSA cryptosystem

Implementation of vedic divider on RSA cryptosystem

Integration of Cryptography Standards and Steganography for Secure Communication

A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate

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