A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate

Anitha, R.; Deshmukh, Neha; Agarwal, Prashant; Sahoo, Sarat Kumar; Karthikeyan, S. Prabhakar; Reglend, I. Jacob

doi:10.1109/iccpct.2015.7159505

Cited by 16 publications

(3 citation statements)

References 11 publications

(8 reference statements)

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“…Anitha et al [18] designed and implemented a Vedic Multiplier and Reversible Logic Gates in the multiply and accumulate unit. The Urdhava Triyagbhayam sutra was used to develop a Vedic multiplier, and a reversible logic gate was used to develop an adder.…”

Section: Literature Surveymentioning

confidence: 99%

Design of high speed approximate multipliers with inexact compressor adder

Sudharani¹,

Sreenivasulu²

2021

IJATEE

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In most practical applications, accurate results are unnecessary, hence approximate computation is being used. By using approximate computing the system performance metrics like area, power and speed can be improved. This paper proposes an approximate circuit that was developed by modifying the circuit architecture but not the circuit operation. We propose an approximate multiplier using these approximate circuits, which use AND-OR logic approximation, Wallace tree reduction, and 3:2 inexact additive designs for partial product generation and addition. In this paper, by taking an 8X8 bit multiplication as an example, we show the whole proposed concept. Also, the proposed multipliers will cause substantial improvements in terms of both area and delay. Compared to the conventional multipliers, the AWM1 achieves up to 35.577% reduction in area and 35.224% in delay. AWM2 has an area and delay reductions of up to 48.077% and 36.532% respectively. AWM3 has area savings of up to 48.077% and delay reductions of up to 46.633%. Finally, the AWM4 has area savings of up to 53.846% and delay reductions of up to 56.482%.

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Section: Literature Surveymentioning

confidence: 99%

Design of high speed approximate multipliers with inexact compressor adder

Sudharani¹,

Sreenivasulu²

2021

IJATEE

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“…Features and design constraints of reversible logic. [4][5]  Reversible logic has unique number of outputs and inputs.  Fan-out is restricted.…”

Section: Reversible Gatesmentioning

confidence: 99%

Design and Implementation of Reversible Vedic Multiplier with Trlic

S*,

Bhavani,

Babu

et al. 2020

IJRTE

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The 'Vedic Mathematics' is the name given to the ancient system of mathematics with a unique technique of calculations based on simple rules and principles with which any mathematical problem can be solved with the help of arithmetic, algebra, geometry or trigonometry. In any of the fastest ALU, multiplier play an inevitable role. There is always a demand on high speed multiplier due to the raising limitation on delay. Increasing the speed of a multiplier there are number of new techniques have been implemented in which multiplier using Vedic mathematics are foremost one. The system performance and delay depend on the performance of multiplier used in it. Multiplier are used in different area such as cryptography, image processing application, embedded system application, programmable filter application etc .One of the major techniques to scale back the power dissipation is Reversible logic. There is no loss of data therefore power dissipation is reduced producing distinctive output for fixed input and vice-versa. The main objective of the project is to scale back the TRLIC of the multiplier factor by exploitation of Vedic arithmetic.The proposed methods are designed using VHDL Programming language, simulation and synthesis are done using Cadence RTL compiler in 180nm technology.

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“…A adder unit [2] is a predictable feature of many applications for digital signal processing involving multiplication/accumulation. It is used to operate digital highspeed DSP systems [3][4][5]. DSP has a wide range of uses, including convolution, filtering, and inside objects.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Parallel Adder Using Reversible Logic Gates

Yuvaraj¹,

Gunasekaran²,

Muthukumaran

et al. 2021

Micro-Electronics and Telecommunication Engineering

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Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction of an 8-, 16-, 32-, 64-bit multiplier using the carry-save adder, the Kogge stone adder, and the HNFG adder with the high operating speed of the proposed HNFG gate adder. The architecture of the device and the logic gates which are reversible can be implemented using the Vedic multiplier. The output of the accumulator operation is dependent on the multiplier unit and the adder units. Here, the development of a multiplier and an adder can be built using reversible gates to achieve high operating speeds, and the use of a Vedic multiplier for greater efficiency. Also fewer area and partial elements are used. A comparative study is being conducted between the conventional [1] and the Kogge stone adder based on HNFG. Finally, it has been shown that the proposed HNFG gate with multiplier adder has a relatively high-speed over the conventional method. The whole process of simulation and synthesis is done using Xilinx 14.7 tool.

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A 32 BIT MAC unit design using Vedic multiplier and reversible logic gate

Cited by 16 publications

References 11 publications

Design of high speed approximate multipliers with inexact compressor adder

Design of high speed approximate multipliers with inexact compressor adder

Design and Implementation of Reversible Vedic Multiplier with Trlic

FPGA Implementation of Parallel Adder Using Reversible Logic Gates

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