An efficient FPGA random number generator using LFSRs and cellular automata

Cerda, Juan C.; Martinez, Chris D.; Comer, Jonathan M.; Hoe, David H. K.

doi:10.1109/mwscas.2012.6292169

Cited by 12 publications

(7 citation statements)

References 7 publications

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“…In terms of area, the PRNGs based on cellular automata [62,64,67] have the lowest resource occupation of FPGA, if we compare them to the other ones (see Figure 16a). By comparison, the PRNG based on LFSR [41] is 76 times larger.…”

Section: Hardware Comparisonmentioning

confidence: 99%

“…However, some drawbacks of this implementation are revealed during statistical evaluation, which can be surpassed only if the two PRNGs are clocked at different clock frequencies. This is why a new solution is presented in [62].…”

mentioning

confidence: 99%

“…In practice, the input rules of each neighbor cell are also a second CA which is executed in parallel with the main cellular automata. Remark that, despite SPA gives a better throughput than the LFSR/HCA combination PRNG [62], it fails to pass the statistical tests of and 9-bits). However, NFSR is known for its short period length.…”

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confidence: 99%

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Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

Bakiri

Guyeux

Couchot

et al. 2018

Computer Science Review

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Random number generation refers to many applications such as simulation, numerical analysis, cryptography etc. Field Programmable Gate Array (FPGA) are reconfigurable hardware systems, which allow rapid prototyping. This research work is the first comprehensive survey on how random number generators are implemented on Field Programmable Gate Arrays (FPGAs). A rich and upto-date list of generators specifically mapped to FPGA are presented with deep technical details on their definitions and implementations. A classification of these generators is presented, which encompasses linear and nonlinear (chaotic) pseudo and truly random number generators. A statistical comparison through standard batteries of tests, as well as implementation comparison based on speed and area performances, are finally presented.

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Section: Hardware Comparisonmentioning

confidence: 99%

mentioning

confidence: 99%

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Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

Bakiri

Guyeux

Couchot

et al. 2018

Computer Science Review

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“…RTL code and ASM chart are used to simplify a complex digital circuit design on rearranged components and algorithm that needs to be counted. Besides, those methods are extremely used to describe any cycle-driven RTL circuit [13]. Each state may have several functions which can run in concurrent fashion.…”

Section: Rt L Code and Asm Chartmentioning

confidence: 99%

A Mixture between Rule 90 and Rule 150 Cellular Automata as a Test Pattern Generator

Alawey¹

2018

ETJ

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Built-in Self-test (BIST) is one of integrated circuit (IC) testing techniques that can be used as a pseudo-random generator for the Circuit Under Test (CUT). This paper introduces the design and simulation of a 4-bit test pattern generator (TPG) using a one dimension Linear Hybrid Cellular Automata (LHCA) with a mixture of rule 90 and 150. LHCA is an enhancement from Linear Feedback Shift Register (LFSR) which can have more random test vectors and improving the cycle length. Design and simulation have been performed using Quartus II and Model Sim software.

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“…For instance, seed extraction from different natural phenomena has been proposed, such as nuclear decay or thermal noise [40]. FPGA-based designs of LFSRs are numerous in the literature; see, for instance, [41–43]. Second, True Random Number Generators (TRNGs) utilize a physical process for generating random data.…”

Section: Future Workmentioning

confidence: 99%

Extending the IEEE 802.15.4 Security Suite with a Compact Implementation of the NIST P-192/B-163 Elliptic Curves

Piedra

Braeken

Touhafi

2013

Sensors

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Typically, commercial sensor nodes are equipped with MCUsclocked at a low-frequency (i.e., within the 4–12 MHz range). Consequently, executing cryptographic algorithms in those MCUs generally requires a huge amount of time. In this respect, the required energy consumption can be higher than using a separate accelerator based on a Field-programmable Gate Array (FPGA) that is switched on when needed. In this manuscript, we present the design of a cryptographic accelerator suitable for an FPGA-based sensor node and compliant with the IEEE802.15.4 standard. All the embedded resources of the target platform (Xilinx Artix-7) have been maximized in order to provide a cost-effective solution. Moreover, we have added key negotiation capabilities to the IEEE 802.15.4 security suite based on Elliptic Curve Cryptography (ECC;. Our results suggest that tailored accelerators based on FPGA can behave better in terms of energy than contemporary software solutions for motes, such as the TinyECC and NanoECC libraries. In this regard, a point multiplication (PM) can be performed between 8.58- and 15.4-times faster, 3.40- to 23.59-times faster (Elliptic Curve Diffie-Hellman, ECDH) and between 5.45- and 34.26-times faster (Elliptic Curve Integrated Encryption Scheme, ECIES). Moreover, the energy consumption was also improved with a factor of 8.96 (PM).

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An efficient FPGA random number generator using LFSRs and cellular automata

Cited by 12 publications

References 7 publications

Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

A Mixture between Rule 90 and Rule 150 Cellular Automata as a Test Pattern Generator

Extending the IEEE 802.15.4 Security Suite with a Compact Implementation of the NIST P-192/B-163 Elliptic Curves

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