Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

Bakiri, Mohammed; Guyeux, Christophe; Couchot, Jean-François; Oudjida, Abdelkrim K.

doi:10.1016/j.cosrev.2018.01.002

Cited by 78 publications

(42 citation statements)

References 96 publications

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“…Entropy 2018, 20, x FOR PEER REVIEW 5 of 10 according to (17). The bifurcation graph shown in Figure 2 suggests that for these values of and , = 1.75 is the transition border from bounded to unbounded chaos.…”

Section: Chaotic Signal Formationmentioning

confidence: 99%

“…Entropy 2018, 20, x FOR PEER REVIEW 2 of 10 loop (PLL) device in the chaotic regime for random number generation is considered. The use of PLL circuits for the generation of random numbers in reconfigurable hardware platforms was extensively studied, where the randomness was extracted from the intrinsic jitter of the synthesized clock signal by the PLL [14][15][16][17]. In this paper, the PLL device is used to generate bounded and unbounded chaos, as described in [18,19].…”

Section: Chaotic Systemmentioning

confidence: 99%

“…To put the system in chaos, the normalized natural frequency β and the normalized modulation frequency Ω m are chosen to be 0.56 and 0.9, respectively, although many other combinations of parameter values for chaos can be found by experimenting with the numerical solver. Then, a is changed linearly by varying the m parameter according to (17). The bifurcation graph shown in Figure 2 suggests that for these values of β and Ω m , m = 1.75 is the transition border from bounded to unbounded chaos.…”

Section: Chaotic Signal Formationmentioning

confidence: 99%

See 2 more Smart Citations

An Analysis of Deterministic Chaos as an Entropy Source for Random Number Generators

Demir

Ergün

2018

Entropy

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This paper presents an analytical study on the use of deterministic chaos as an entropy source for the generation of random numbers. The chaotic signal generated by a phase-locked loop (PLL) device is investigated using numerical simulations. Depending on the system parameters, the chaos originating from the PLL device can be either bounded or unbounded in the phase direction. Bounded and unbounded chaos differs in terms of the flatness of the power spectrum associated with the chaotic signal. Random bits are generated by regular sampling of the signal from bounded and unbounded chaos. A white Gaussian noise source is also sampled regularly to generate random bits. By varying the sampling frequency, and based on the autocorrelation and the approximate entropy analysis of the resulting bit sequences, a comparison is made between bounded chaos, unbounded chaos and Gaussian white noise as an entropy source for random number generators.

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Section: Chaotic Signal Formationmentioning

confidence: 99%

Section: Chaotic Systemmentioning

confidence: 99%

Section: Chaotic Signal Formationmentioning

confidence: 99%

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An Analysis of Deterministic Chaos as an Entropy Source for Random Number Generators

Demir

Ergün

2018

Entropy

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“…As mentioned in Section III, the channel has been simulated defining a finite state machine through a counter threshold. The core module used to realize the emulation of the channel was the so-called burst adder implementing an LFSR, which is a linear recurrent generator [36]. To implement an LFSR, a sequence of shift registers is needed, generating one bit for each iteration of the algorithm.…”

Section: B Comparison Of the Fpga Implementation With A Cpu Onementioning

confidence: 99%

Recent Results on the Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

Travan

Vatta

Babich

2020

J. commun. softw. syst. (Online)

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The behaviour of a transmission channel may be simulated using the performance abilities of current generation multiprocessing hardware, namely, a multicore Central Processing Unit (CPU), a general purpose Graphics Processing Unit (GPU), or a Field Programmable Gate Array (FPGA). These were investigated by Cullinan et al. in a recent paper (published in 2012) where these three devices capabilities were compared to determine which device would be best suited towards which specific task. In particular, it was shown that, for the application which is objective of our work (i.e., for a transmission channel simulation), the FPGA is 26.67 times faster than the GPU and 10.76 times faster than the CPU. Motivated by these results, in this paper we propose and present a direct hardware emulation. In particular, a Cyclone II FPGA architecture is implemented to simulate a burst error channel behaviour, in which errors are clustered together, and a burst erasure channel behaviour, in which the erasures are clustered together. The results presented in the paper are valid for any FPGA architecture that may be considered for this scope.

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“…Real-time analysis of binary sequence produced by the generator and randomness testing based on NIST tests as an application in LabVIEW was proposed [11]. An extensive classification of hardware random number generators (linear and non-linear) on FPGA is presented and statistical comparison of the test results produced [12], also the resistance to various forms of cryptanalysis like correlation attacks and algebraic ones are improved. A three-tier security scheme by Embedding unique signatures with minimalistic hardware or area overhead using a PRNG is proposed by Manoj Reddy et.al.…”

Section: Literature Surveymentioning

confidence: 99%

Design And Analysis of Analog TRNG Using Sample and Hold Circuit

Aksshaya¹,

Madhura²,

Nivethashri³

et al. 2018

IJET

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Implementation of analog True random number generators is inevitable in almost all the security applications and encryption protocols nowadays. Although many digital True Random Number Generators are available, we proposed a method of random number generation using analog module of mixed signals. In actual fact generation of True Random Numbers is by utilizing the sample and hold circuit which is controlled by another random clock source, and a post processing circuit for generation of unpredictable binary sequence of numbers. The primary input source is an analog signal, essentially highly random noise from the external environment. The high unpredictability, less resource and simple circuit design are some highlights of the proposed work. Finally, the randomness is evaluated using NIST test suites and results are plotted and analyzed.

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Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

Cited by 78 publications

References 96 publications

An Analysis of Deterministic Chaos as an Entropy Source for Random Number Generators

An Analysis of Deterministic Chaos as an Entropy Source for Random Number Generators

Recent Results on the Implementation of a Burst Error and Burst Erasure Channel Emulator Using an FPGA Architecture

Design And Analysis of Analog TRNG Using Sample and Hold Circuit

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