An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Krill, B.; Ahmad, Afandi; Amira, Abbes; Rabah, Hassan

doi:10.1016/j.image.2010.04.005

Cited by 28 publications

(8 citation statements)

References 25 publications

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“…performance has also been examined. By implementing DPR technique in this research study, better area utilisation and minimum power consumption can be achieved as well as better maximum frequency [50], [107], [143].…”

Section: Summary 131mentioning

confidence: 95%

Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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A AbstractRecently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

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Section: Summary 131mentioning

confidence: 95%

Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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“…The DPR feature available in the latest FPGAs, provides an extended re-programmability to the designer to dynamically alter the design modules in the Partially Reconfigurable Region (PRR) of the FPGA keeping the static region unchanged. The DPR allows the alteration of dynamically reconfigurable region (DRR) of FPGA by loading the bit files of Partially Reconfigurable Modules(PRM) keeping the other regions of FPGA fully functional [5,7,8]. Thus, DPR allows power optimization in such devices by dynamically configuring only the modules performing the intended applications while keeping other power hungry modules turned off.…”

Section: Dynamic Partial Reconfiguration Of Fpga and Dpr Flowmentioning

confidence: 99%

Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA

Acharya¹,

Rani²

2018

IJRES

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<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.</span>

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“…The fundamental actions of the algorithms used in medical image processing applications involve matrix operations, mostly matrix transforms include Fast Fourier Transform (FFT), Discrete Wavelet Transform (DWT), some recently developed transforms such as finite Radon, curvelet and ridgelet transform [6][7]. Therefore, there is a real need for high-performance systems, whilst keeping architectures flexible to allow for quick upgradeability with real-time applications [2].…”

Section: Introductionmentioning

confidence: 99%

“…The capability to develop a programmable circuit architecture with the flexibility of computational, memory, speed and power requirement, FPGAs seem an ideal candidate to be proposed as a hardware technology for prototype a simple, moderate and complex applications [2], [10]. Indeed, other advantages offered by FPGAs are massive parallelism capabilities, multimillion gate counts and special low-power packages [6,11].…”

Section: Introductionmentioning

confidence: 99%

Algorithm development and hardware implementation for medical image compression system: a review

Ja’afar

Ahmad

2020

IJEECS

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<span>In the high-tech world, medical imaging is very important to diagnose and analyze illness inside human body. The increasing number of patients annually has continuously growth the amount of medical imaging data generated and directly causes a demand for data storage. Generally, medical images are rich with data, where these data are important for diagnosing purpose. However, some of the data represents redundant information and sometimes can be discarded. Thus, the research area on medical image compression dealing with three-dimensional (3-D) modalities need to be given more attention and exploration. The algorithm development using wavelet transform with software implementation are the famous topics explored among researchers, whilst fewer works have been done in utilizing curvelet transform in medical image compression. Along with that, very limited hardware implementation of 3-D medical image compression is discovered. In term of performance evaluation, most of the previous works conducted objective test compared with subjective test. To fill in this gap, medical image compression system will be reviewed, with the aim to identify the recent method used in medical image compression system. This paper thoroughly scrutinizes the recent advances in medical image compression mainly in terms of compression method, algorithm development with software and hardware implementations and performance evaluation. In conclusion, the overall picture of the medical image compression landscape, where most of the researchers more focused on algorithm development or software implementations without having the combination of software and hardware implementations.</span>

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An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

Cited by 28 publications

References 25 publications

Efficient reconfigurable architectures for 3D medical image compression

Efficient reconfigurable architectures for 3D medical image compression

Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA

Algorithm development and hardware implementation for medical image compression system: a review

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