An efficient clocking scheme for quantum-dot cellular automata

Goswami, Mrinal; Mondal, Anindan; Mahalat, Mahabub Hasan; Sen, Bibhash; Sikdar, Biplab K.

doi:10.1080/21681724.2019.1570551

Cited by 37 publications

(19 citation statements)

References 25 publications

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“…This critical issues was resolved in [50] (shown in Figure 5(b)) with an added complication of multi-layer wire crossing in the design. Later, a robust and scalable scheme with coplanar wire crossing was proposed in [51]. With the added benefit of three-directional information flow in any particular clock zone, it lacks in continuous underlying wire connection for clock zone 3( Figure 5(c)).…”

Section: Regular Clocking Based Realizationmentioning

confidence: 99%

“…But, multi-layer QCA circuit did not get any significance due to its fabrication complexity. Alter-natively, a coplanar wire crossing based design with three-dimensional information flow was proposed in [51]. However, the wire crossing increases in the underlying clocking circuit due to the complex layout for clock zone 3 in [51].…”

mentioning

confidence: 99%

“…Alter-natively, a coplanar wire crossing based design with three-dimensional information flow was proposed in [51]. However, the wire crossing increases in the underlying clocking circuit due to the complex layout for clock zone 3 in [51]. These points have a notable impact on the buildabilty of the circuit and demands a flexible, scalable and robust clocking scheme with reduced complexity in fabrication.…”

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confidence: 99%

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Regular clocking scheme based design of cost-efficient comparator in QCA

Pal

Noorallahzadeh

Sharma

et al. 2021

IJEECS

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<span>Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.</span>

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Section: Regular Clocking Based Realizationmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Regular clocking scheme based design of cost-efficient comparator in QCA

Pal

Noorallahzadeh

Sharma

et al. 2021

IJEECS

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“…The main benefit of clocking in the QCA circuits lies in the fact that information loss and diminution can be re‐established. In QCA, an electric field helps to produce the clocking mechanism [20,29,30].…”

Section: Qca Backgroundmentioning

confidence: 99%

Systematic cell placement in quantum‐dot cellular automata embedding underlying regular clocking circuit

Bhowmik

Pal

Goswami

et al. 2021

IET Circuits, Devices & Syst

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Quantum‐dot cellular automata (QCA) is gaining worldwide popularity due to its higher device concentration, lower power indulgence, and better switching speed. The information flows in QCA with the polarization state defined by the placement of electrons instead of current flow. The cell interaction principle under the influence of the clocking zone controls the cell placement during QCA circuit design. Most of the designs reported so far used random cell placement, which has no fabricating sense. Moreover, it is equally important for a cell placement algorithm to follow a realistic, regular underlying clocking scheme to maintain proper routing channels. In this regard, a systematic cell placement for the combinational logic circuit in QCA is proposed using the widely accepted underlying regular clocking scheme, universal, scalable and efficient (USE). The proposed method traverses all possible paths of a combinational logic circuit from output to input to build the desired circuit generating the automatic cell layout. A grid of clock zone of USE clock scheme is considered in the initial layout driving different paths of the circuit and finally evolves as the desired circuit. The generated automatic QCA layouts are competitive in occupied area, delay, and its cell count, which advocates the significance of such a scheme.

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“…A Composite Logic Gate (CG) allows the maximum realization of logic functions and reduces the circuit complexity & QCA cost. The use of an underlying regular clocking is essential for the design, considering the timing issue for an error-free and high-performance behavior [18,19].…”

Section: Introductionmentioning

confidence: 99%

Synthesis of composite logic gate in QCA embedding underlying regular clocking

et al. 2021

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Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

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An efficient clocking scheme for quantum-dot cellular automata

Cited by 37 publications

References 25 publications

Regular clocking scheme based design of cost-efficient comparator in QCA

Regular clocking scheme based design of cost-efficient comparator in QCA

Systematic cell placement in quantum‐dot cellular automata embedding underlying regular clocking circuit

Synthesis of composite logic gate in QCA embedding underlying regular clocking

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