An efficient approach to the computation of analytic, pseudo analytic sensitivities and noise in an APL general purpose CAD program

Zein, D.A.; Chang, Cheng

doi:10.1109/mcas.1982.6323804

Cited by 6 publications

(1 citation statement)

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“…Our experience shows that the optimization procedure almost always converges due to the fact that we compute accurate analytic and pseudo analytic sensitivities usiig the adjoint method, [6] . However, in the case of the 48K-bit chip mentioned above, optimization was not required siice all the design criteria were met, and the chip was a first pass design.…”

Section: Analytic Techniques and Algorithmsmentioning

confidence: 99%

A semi-direct method for design verification of array chips

Zein

Engel

Ditlow

[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems

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An experimental general purpose program based on ICD has been created to aid in the design of bipolar array chips. The program consists of a unique automated set of tools that verify the logic function of every chip circuit, determine signal noise margin, and reliability guideline checking for contact studs. The program was originally developed as part of analog and logic design verification tools to audit the design of a 48K-bit bipolar array cache chip prior to release to manufacturing. The analytic tools used consist of the use of a Semi -Di rect method of analysis, a Gray algorithm, and recognition of diffmntial pairs to minimize the number of simulations (DC reruns), and a set of techniques to take into account the peculiarities of bipolar circuits, such as emitter and collector dots, input output loading conditions, differential pairs and the presence of a mixture of digital, sequential, and analog circuits. As a result, the design verification of 60 distinct circuits (books) of the 48K chip took less than 3 CPU minutes on an IBM 3090 computer. This included, among other things, conducting 2" DC simulations or reruns of each book, where n is the number of inputs or fan-ins. Furthermore, output behavioral models representing the basic chip circuits were used as basic leaf models in HLSIM, a Hierarchical Logic Simulator, which was used to simulate the whole 48K-bit array. SummaryThe design of any VLSI chip is at a minimum a very complex task. Chip requirements are typically simple, consisting of the number of bits required, read/write organization, and performance. The realization of the

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Section: Analytic Techniques and Algorithmsmentioning

confidence: 99%