An Efficient and Reliable Watermarking System for IP Protection

Nie, Tingyuan; Toyonaga, Masahiko

doi:10.1093/ietfec/e90-a.9.1932

Cited by 7 publications

(7 citation statements)

References 11 publications

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“…The probability of leaking watermark is lower in the proposed algorithm. When the collusion users are more than 60, the probability in Nie and Toyonaga 25 increases rapidly than that in Schmid et al 26 It is because the use of random number in the generation of secret key. In fact, it is pseudo-random number, which can be found with enumeration.…”

Section: Resistance Against Attacksmentioning

confidence: 92%

Intellectual property protection for FPGA designs using the public key cryptography

Huang

et al. 2019

Advances in Mechanical Engineering

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For the copyright protection in intellectual property reuse technology, we must ensure that when an intellectual property watermark verifier leaks the secret key of an intellectual property watermark system, a malicious attacker could not guess the key to facilitate successful attacks on the watermarks. Therefore, this work proposes a robust intellectual property watermarking algorithm based on elliptic-curve cryptography. The physical layout of intellectual property design is abstracted into a graph with tree structure by using the topology theory. A secure model based on the asymmetric encryption model is proposed to encrypt the watermark positions. The generated graph and a random searching algorithm are used for the distribution of the watermark positions. Finally, the watermarks are inserted by reordering the redundant attributes in the graph. The experiments show that the proposed algorithm will insert more watermark constraints under the same condition. Thus, the probability of coincidence is lower, achieving good reliability. In addition, when the watermarks are impaired due to attacks, the algorithm can restore the original watermarks from the topology graph. In comparison to other algorithms, the proposed algorithm has good performance in watermark capacity and overhead, as well as provides resilience to the typical attacks.

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Section: Resistance Against Attacksmentioning

confidence: 92%

Intellectual property protection for FPGA designs using the public key cryptography

Huang

et al. 2019

Advances in Mechanical Engineering

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“…This section of attacks awaits innovative solutions. Signature embedded by applying constraints in place/ route phase of physical design [8] or through incremental router [37] cannot be verified from an IC fabricated from that marked design. Hence, in order to provide effective security of an IP on SoC, the mark (i.e., watermarks and fingerprints) insertion technique should be resilient against fabrication.…”

Section: Ip Protection In Socmentioning

confidence: 99%

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection

Saha

Sur-Kolay

2011

VLSI Design

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Increased design complexity, shrinking design cycle, and low cost—this three-dimensional demand mandates advent of system-on-chip (SoC) methodology in semiconductor industry. The key concept of SoC is reuse of the intellectual property (IP) cores. Reuse of IPs on SoC increases the risk of misappropriation of IPs due to introduction of several new attacks and involvement of various parties as adversaries. Existing literature has huge number of proposals for IP protection (IPP) techniques to be incorporated in the IP design flow as well as in the SoC design methodology. However, these are quite scattered, limited in possibilities in multithreat environment, and sometimes mutually conflicting. Existing works need critical survey, proper categorization, and summarization to focus on the inherent tradeoff, existing security holes, and new research directions. This paper discusses the IP-based SoC design flow to highlight the exact locations and the nature of infringements in the flow, identifies the adversaries, categorizes these infringements, and applies strategic analysis on the effectiveness of the existing IPP techniques for these categories of infringements. It also clearly highlights recent challenges and new opportunities in this emerging field of research.

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“…Security tags including physical unclonable functions (PUFs) have been proposed for implementing unique extrinsic IC identifiers [1,2]. Watermarking is a comprehensive mechanism implemented to protect IP which is roughly categorized into constraint-based methods [3,4] or additive methods [5,6]. However, watermarking techniques do not facilitate the tracing process of illegally resold IPs and therefore cannot provide IP protection for buyers.…”

Section: Introductionmentioning

confidence: 99%

Circuit partitioning based fingerprinting method for IP protection

Nie

Sun

et al. 2013

IEICE Electron. Express

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Abstract:The continuously widening design productivity gap in the past few decades gives high incentives to counterfeiting ICs. Existing intellectual property (IP) protection schemes demand high overheads, and some techniques like watermarking do not facilitate tracing of illegal users. In this letter,we propose a novel fingerprinting method based on post-processing on circuit partitions. We evaluate our method on the ISPD98 benchmark suite. The experimental results demonstrate the effectiveness of the proposal. The fingerprinting design is distinct because the Hamming distance between fingerprinted IP designs is large enough to resist a collusion attack.

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An Efficient and Reliable Watermarking System for IP Protection

Cited by 7 publications

References 11 publications

Intellectual property protection for FPGA designs using the public key cryptography

Intellectual property protection for FPGA designs using the public key cryptography

SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection

Circuit partitioning based fingerprinting method for IP protection

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