An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2 )

Rashidi, Bahram; Sayedi, Sayed Masoud; Farashahi, Reza Rezaeian

doi:10.1016/j.vlsi.2016.05.006

Cited by 10 publications

(11 citation statements)

References 20 publications

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“…More details for computation of λ (k) i,j and normal basis multiplication is presented in [38] and [39]. The GNB multiplication of C = A × B can also be computed by the following approach [7].…”

Section: • Multiplication In F 2 Mmentioning

confidence: 99%

“…are computed similarly by one bit right cyclic shift of inputs [40]- [41]. Normal basis multiplication approaches and comprehensive comparisons for GNB and ONB multiplier structures can be found in [39]- [41].…”

Section: • Multiplication In F 2 Mmentioning

confidence: 99%

“…In the design of the field multiplier in the ECC structure, to balance the delay among the stages and to obtain a minimum over all delay, the logical effort technique can be applied. A hardware implementation of the logical effort in the cryptographic applications can be found in [39] and [57]. This technique is suitable for high-speed hardware implementation of the ECC.…”

Section: • Logical Effortmentioning

confidence: 99%

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A Survey on Hardware Implementations of Elliptic Curve Cryptosystems

Rashidi

2017

Preprint

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In the past two decades, Elliptic Curve Cryptography (ECC) have become increasingly advanced. ECC, with much smaller key sizes, offers equivalent security when compared to other asymmetric cryptosystems. In this survey, an comprehensive overview of hardware implementations of ECC is provided. We first discuss different elliptic curves, point multiplication algorithms and underling finite field operations over binary fields F2m and prime fields Fp which are used in the literature for hardware implementation. Then methods, steps and considerations of ECC implementation are presented. The implementations of the ECC are categorized in two main groups based on implementation technologies consist of field programmable gate array (FPGA) based implementations and application specific integrated circuit (ASIC) implementations. Therefore, in these categories to have a better presentation and comparison, the implementations are presented and distinguished based on type of finite fields. The best and newest structures in the literature are described in more details for overall presentation of architectures and approaches in each group of implementations. High-speed implementation is an important factor in the ECC applications such as network servers. Also in smart cards, Wireless Sensor Networks (WSN) and Radio Frequency Identification (RFID) tags require to low-cost and lightweight implementations. Therefore, implementation methods related to these applications are explored. In addition, a classification of the previous works in terms of scalability, flexibility, performance and cost effectiveness is provided. Finally, some words and techniques about future works that should be considered are provided.

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Section: • Multiplication In F 2 Mmentioning

confidence: 99%

Section: • Multiplication In F 2 Mmentioning

confidence: 99%

Section: • Logical Effortmentioning

confidence: 99%

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A Survey on Hardware Implementations of Elliptic Curve Cryptosystems

Rashidi

2017

Preprint

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“…(i) A full-custom efficient hardware structure for the point multiplication on BECs for ASIC applications. (ii) The PA and PD computations are scheduled by only one digitserial multiplier, and our previously reported digit-serial GNB multiplier [20,21] is used for implementation. In this multiplier, a structural very large-scale integration (VLSI) design of the XOR tree is presented based on logical effort technique and by using an optimised four-input XOR gate.…”

Section: Introductionmentioning

confidence: 99%

“…The BECs provide complete addition formulas for binary elliptic curves that make them attractive for implementation, and are intrinsically resistant to simple power analysis [10]. The main contributions in this work are as follows: (i) A full‐custom efficient hardware structure for the point multiplication on BECs for ASIC applications. (ii) The PA and PD computations are scheduled by only one digit‐serial multiplier, and our previously reported digit‐serial GNB multiplier [20, 21] is used for implementation. In this multiplier, a structural very large‐scale integration (VLSI) design of the XOR tree is presented based on logical effort technique and by using an optimised four‐input XOR gate.…”

Section: Introductionmentioning

confidence: 99%

Full‐custom hardware implementation of point multiplication on binary Edwards curves for application‐specific integrated circuit elliptic curve cryptosystem applications

Rashidi

Sayedi

Farashahi

2017

IET Circuits, Devices & Syst

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This study presents an efficient and high-speed very large-scale integration implementation of point multiplication on binary Edwards curves over binary finite field GF(2 m) with Gaussian normal basis representation. The proposed implementation is a low-cost structure constructed by one digit-serial multiplier. In the proposed scheduling of point multiplication, the field multiplier is busy during point addition and point doubling computations. In the field multiplier structure, by using the logical effort technique the delay is optimally decreased and the drive ability of the circuit in the point multiplication architecture is increased. Also, to reduce area and number of transistors of the point multiplication circuit, all components are selected based on low-cost structures. The design is implemented in 0.18 μm CMOS technology over binary finite field GF(2 233). The results confirm the validity of the proposed structure and its high performance in terms of delay and area cost.

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