A Survey on Hardware Implementations of Elliptic Curve Cryptosystems

Rashidi, Bahram

doi:10.48550/arxiv.1710.08336

Cited by 3 publications

(3 citation statements)

References 125 publications

(321 reference statements)

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“…One part of ECC consists of elliptic curves defined over a finite field of positive integers modulo a prime number p. Curve25519 is one of the fastest and mostly commonly used elliptic curves defined with p = 2 255 − 19 [Ber06]. Operations on points of the elliptic curve consist of field operations, the most time-consuming of which is modular inversion with modulus p. As a result, many ECC implementations use different coordinate systems for most of the computation to minimize the number of inversions required [Ras17].…”

Section: Modular Inversionmentioning

confidence: 99%

Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion

Sreedhar

Horowitz

Torng

2022

TCHES

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The extended GCD (XGCD) calculation, which computes Bézout coefficients ba, bb such that ba ∗ a0 + bb ∗ b0 = GCD(a0, b0), is a critical operation in many cryptographic applications. In particular, large-integer XGCD is computationally dominant for two applications of increasing interest: verifiable delay functions that square binary quadratic forms within a class group and constant-time modular inversion for elliptic curve cryptography. Most prior work has focused on fast software implementations. The few works investigating hardware acceleration build on variants of Euclid’s division-based algorithm, following the approach used in optimized software. We show that adopting variants of Stein’s subtraction-based algorithm instead leads to significantly faster hardware. We quantify this advantage by performing a large-integer XGCD accelerator design space exploration comparing Euclid- and Stein-based algorithms for various application requirements. This exploration leads us to an XGCD hardware accelerator that is flexible and efficient, supports fast average and constant-time evaluation, and is easily extensible for polynomial GCD. Our 16nm ASIC design calculates 1024-bit XGCD in 294ns (8x faster than the state-of-the-art ASIC) and constant-time 255-bit XGCD for inverses in the field of integers modulo the prime 2255−19 in 85ns (31× faster than state-of-the-art software). We believe our design is the first high-performance ASIC for the XGCD computation that is also capable of constant-time evaluation. Our work is publicly available at https://github.com/kavyasreedhar/sreedhar-xgcd-hardware-ches2022.

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Section: Modular Inversionmentioning

confidence: 99%

Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion

Sreedhar

Horowitz

Torng

2022

TCHES

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“…It is also worth mentioning that ECC-based cryptography protocols can be developed using finite fields with binary characteristics GF (2 m ). An interested reader is referred to [42], [43], [44], and [45] for further information about such proposals. This work presents an efficient EC cryptographic processor over a general prime field.…”

Section: Introductionmentioning

confidence: 99%

EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

2023

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Elliptic Curve Cryptography (ECC) based security protocols require much shorter key space which makes ECC the most suitable option for resource-limited devices as compared to the other public key cryptography (PKC) schemes. This paper presents a highly efficient area-delay optimized ECC crypto processor over the general prime field (F p ). It is structured on a new novel finite field multiplier (FFM) where several optimization techniques have been incorporated to shorten the latency and hardware resource consumption. The proposed FFM architecture is embedded with a finite field adder/subtractor (FFAS) unit which is utilized to perform FFAS operations instead of deploying a dedicated unit. The Common Z (Co-Z) coordinates with the Montgomery ladder method are used to compute point multiplication, a core operation in all ECC-based crypto protocols. The work also proposes an efficient scheduling strategy to execute low-level finite field arithmetic primitives with minimum latency on the employed finite field arithmetic units. Due to these techniques, the proposed ECC processor is optimized for hardware resources, latency, and throughput. It is captured in Verilog-HDL, synthesized, and implemented on Virtex-7, Kintex-7, and Virtex-6 FPGA platforms using Xilinx Vivado and ISE Design Suite tools. On the Virtex-7 FPGA platform, it computes a single 256-bit scalar multiplication primitive in 0.7 ms, consumes just 6.2K slices, and delivers a throughput of 1428 operations per second. The implementation results show that it is a highly efficient design outperforming the state-of-the-art by providing a better area-delay product and higher efficiency. Therefore, it has the potential to be deployed in many applications where both latency and resource requirements are critical.INDEX TERMS Elliptic curve cryptography (ECC), finite field multiplication, field programmable gate array (FPGA), hardware acceleration, finite field arithmetic.

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“…Like the extensive use of ECCs as mentioned in the [9] survey research on ECC hardware implementation, constructing various arithmetic operations efficiently in ECC circuits has become increasingly crucial as hardware and quantum computing research have evolved. In this research, the ECC implementations are categorized into two main groups based on their implementation technologies: field programmable gate array (FPGA)-based implementations [10] and application-specific integrated circuit (ASIC)-based implementations [11].…”

Section: Introductionmentioning

confidence: 99%

Depth-Optimization of Quantum Cryptanalysis on Binary Elliptic Curves

et al. 2023

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This paper presents quantum cryptanalysis for binary elliptic curves from a time-efficient implementation perspective (i.e., reducing the circuit depth), complementing the previous research that focuses on the space-efficiency perspective (i.e., reducing the circuit width). To achieve depth optimization, we propose an improvement to the existing circuit implementation of the Karatsuba multiplier and FLT-based inversion, then construct and analyze the resource in the Qiskit quantum computer simulator. The proposed multiplier architecture, which improves the quantum Karatsuba multiplier from the previous study, reduces the depth and yields a lower number of CNOT gates that bound to O(n log 2 (3) ) while maintaining a similar number of Toffoli gates and qubits. Furthermore, our improved FLT-based inversion reduces CNOT count and overall depth, with a tradeoff of higher qubit size. Finally, we employ the proposed multiplier and FLTbased inversion for performing quantum cryptanalysis of binary point addition as well as the complete Shor's algorithm for the elliptic curve discrete logarithm problem (ECDLP). As a result, apart from depth reduction, we are also able to reduce up to 90% of the Toffoli gates required in a single-step point addition compared to prior work, leading to significant improvements and giving new insights on quantum cryptanalysis for a depth-optimized implementation.

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A Survey on Hardware Implementations of Elliptic Curve Cryptosystems

Cited by 3 publications

References 125 publications

Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion

Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion

EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor

Depth-Optimization of Quantum Cryptanalysis on Binary Elliptic Curves

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