An Efficient and Flexible FPGA Implementation of a Face Detection System

Fekih, Hichem Ben; Elhossini, Ahmed; Juurlink, Ben

doi:10.1007/978-3-319-16214-0_20

Cited by 3 publications

(2 citation statements)

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“…Verilog HDL is one of the most widely used languages for implementing the design structure for Application Specific Integrated Circuit (ASIC) and FPGA-based designs [5]. Verilog HDL describes designs in various abstraction style, for example, gate, data-flow, and behavioural levels.…”

Section: Introductionmentioning

confidence: 99%

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Validation of the Proposed Hardness Analysis Technique for FPGA Designs to Improve Reliability and Fault-Tolerance

Khatri¹,

Hayek²,

̈ok³

2018

ijacsa

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Reliability and fault tolerance of FPGA systems is a major concern nowadays. The continuous increase of the system's complexity makes the reliability evaluation extremely difficult and costly. Redundancy techniques are widely used to increase the reliability of such systems. These techniques provide a large area & time overheads which cause more power consumption and delay, respectively. An experimental evaluation method is proposed to find critical nodes of the FPGA-based designs, named "hardness analysis technique" under the proposed RASP-FIT tool. After finding the critical nodes, the proposed redundant model is applied to those locations of the design and the code is modified. The modified code is functionally equivalent and is more hardened to the soft-errors. An experimental setup is developed to verify and validate the criticality of these locations found by using hardness analysis. After applying redundancy to those locations, the reliability is evaluated concerning failure rate reduction. Experimental results on ISCAS'85 combinational benchmarks show that a min-max range of failure reduction (14%-85%) is achieved compared to the circuit without redundancy under the same faulty conditions, which improves reliability.

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Section: Introductionmentioning

confidence: 99%

“…T f ault = P i × nSec × F copy (5) Where T f ault is the total number of fault injected per experiment for each fault model, P i is the number of patterns considered, i.e. 500, nSec is the number of faulty copies of SUT and F copy is the number of faults selected and activated per copy of SUT during the experiment.…”

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confidence: 99%