An Efficient and Fast VLIW Compression Scheme for Stream Processor

Abstract

Stream processor has been widely used in multimedia processing because of the high performance gained by parallelism. In order to achieve higher parallelism, the stream processor employs large width structure of VLIW (very long instruction word, VLIW) and multiple parallelizable instructions are organized into one VLIW. Because the width of VLIW is fixed, there are a large number of empty operations (non-operation, NOP) filled in VLIW, which results in serious code size expansion problem. Aiming at this issue, the horizontal code compression and vertical code compression methods are applied on the VLIW of stream processor respectively. First the VLIW is divided into several subfields according to the logic characteristics of VLIW instruction, then the horizontal code compression scheme which based on Huffman coding is applied on each subfield and this method can achieve approximately 78% code size reduction on average. However, the extra-long time required to decode the compressed VLIW before instruction execution may cause system performance penalty. In order to reduce the decompression time consumption, the vertical compression scheme is proposed. The vertical compression can reduce the code size nearly 70% by deleting the NOPs of VLIW in vertical direction. Furthermore the VLIW after vertical compression can be executed directly without decompression operation by using banked instruction memory. Specifically, the vertical compression can compress stream processor VLIW code size significantly and without any negative influence on performance.

Dynamic fault-tolerant VLIW processor with heterogeneous Function Units

“…Note that, this is the case for any approach that exploits idle slots. However, as other benchmark analysis have shown, high ILPs are not common and the number of NOPs is usually significantly large [21].…”

Research on Compilation Methods for Fixed Iteration Count Loop Dual-Mode Unrolling in VLIW Architectures

“…Architectures with multiple types of register resources have multiple types of registers to support different types of instructions and operations, with the goal of improving the flexibility and performance of processor to meet different application requirements. These architectures include VLIW (Very Long Instruction Word) architecture [1]- [2], EPIC (Explicitly Parallel Instruction Computing) architecture [3], etc. Among them, VLIW architecture is a kind of parallel architecture that maximize instruction-level parallelism [2] to improve performance.…”

“…4. Multimedia Processing [1] and related domains. Therefore, harnessing the performance advantages of VLIW processors is of paramount importance in these fields.…”

Selective Code Duplication for Soft Error Protection on VLIW Architectures

“…VLIW architectures have been exploited in state-of-the-art embedded systems such as the Xtensa Processor and Accelerated Processing Unit (APU) [12][13][14]. VLIW architectures can be used as co-processors [15] that accelerate kernel parts of a program or customized for IP cores for next-generation mobile devices, home entertainment products, and stream processors [16].…”