Selective Code Duplication for Soft Error Protection on VLIW Architectures

Abstract

Very Long Instruction Word, or VLIW, architectures have received much attention in specific-purpose applications such as scientific computation, digital signal processing, and even safety-critical systems. Several compilation techniques for VLIW architectures have been proposed in order to improve the performance, but there is a lack of research to improve reliability against soft errors. Instruction duplication techniques have been proposed by exploiting unused instruction slots (i.e., NOPs) in VLIW architectures. All the instructions cannot be replicated without additional code lines. Additional code lines are required to increase the number of duplicated instructions in VLIW architectures. Our experimental results show that 52% performance overhead as compared to unprotected source code when we duplicate all the instructions. This considerable performance overhead can be inapplicable for resource-constrained embedded systems so that we can limit the number of additional NOP instructions for selective protection. However, the previous static scheme duplicates instructions just in sequential order. In this work, we propose packing-oriented duplication to maximize the number of duplicated instructions within the same peroformance overhead bounds. Our packing-oriented approach can duplicate up to 18% more instructions within the same performance overheads compared to the previous static duplication techniques.

Dynamic fault-tolerant VLIW processor with heterogeneous Function Units

“…To reduce the additional instructions inserted in the code, approaches do not duplicate all instructions or implement the comparisons in hardware. For instance, a packing-oriented duplication is proposed, compared to the common sequential order, to maximize the number of duplicated instructions within the same performance overhead bound [26]. Instruction duplication and scheduling is performed by the compiler, while the comparison is performed by the hardware [27,9].…”

An Ultra-Low-Cost Soft Error Protection Scheme Based on the Selection of Critical Variables

“…However, modular redundancy schemes need to modify hardware architecture, such as additional modules and validation logic, so it is inappropriate for resource-constrained embedded systems. Software-level redundancy schemes have been presented for soft error protection without hardware modification [26]. For instance, instructions are duplicated, and soft errors can be detected through additional "COMPARE" instructions before being used.…”

Research on Compilation Methods for Fixed Iteration Count Loop Dual-Mode Unrolling in VLIW Architectures

“…2. High-Performance Computing [6]- [7]. VLIW processors offer higher computational throughput and parallelism by simultaneously executing multiple computational operations.…”