An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance

Abstract

We have developed a hop-based complete detailed router ROAD-HOP that uses the Bump & Refit (£ ¥ ¤ § ¦) approach to route a FPGA circuit in a near-optimal manner. This approach is based on generating a minimum-spanning tree (MST) from the complete pin-topin graph of each net with each edge cost based on a combination of its contribution to the net length, channel congestion and potential average "bumping" cost in the channels in which the edge lies. Using the MST, a hop-based routing of each net is performed that attempts to minimize the combination of net length, number of hops and total number of tracks needed in the FPGA. Given each net's global route, a FPGA detailed router can minimize net delays by minimizing the number of hops or equivalently the number of track switchings in complex switchboxes of current FPGAs-hopbased routing can model routing using complex switchboxes. By minimizing the number of hops and total net length, ROAD-HOP minimizes net delay. Note that ROAD-HOP can only be compared to another detailed router and we compare it to the best previous detailed router SEGA for the VPR architecture. We use the output of the VPR global router as input to both ROAD-HOP and SEGA. Our new algorithm achieves significantly better results than SEGA with respect to the number of tracks needed and the circuit speed. Across a number of benchmark circuits, our algorithm needs about 8% fewer tracks than SEGA. Furthermore, the average net delay of the routing generated by our algorithm is 34% less than that of SEGA, and is 52% less for the longest net.

SAT based solutions for detailed routing of island style FPGA architectures

“…The internal connection topology of a Wilton switch decides which tracks the segments S 0 ðAÞ and S 1 ðAÞ may be assigned to. The possible track assignments, represented as ordered pairs (left, top) are (0,0), (1,4), (2,3), (3,2) and (4,1) SwitchCon wil ðS 0 ðAÞ; S 1 ðAÞÞ:…”

“…Three nodes labelled A, B, and C have been created for nets n A , n B , and n C respectively. The edges AB, BC, and AC have been added to the graph because of sharing of CB(0,3) between net n A and n B , CB (3,2) between net n B and n C and CB(2,1) between n A and n C respectively. The resultant graph is shown in Fig.…”

“…In ROAD global routes of prior-routed nets are not changed but their assignments are altered in order to make space for the current net to be routed. ROAD-HOP [3] is a hop-based FPGA detailed routing technique which also follows the Bump & Refit (B & R) approach. All these approaches implement sequential routing and rely on various heuristics to overcome the net ordering problem.…”

Graph colouring based multi pin net detailed routing for FPGA using SAT

“…ROAD [8] is a detailed router that explores the solution space using an approach called Bump & Refit (B & R) in which the global routes of prior-routed nets are not changed but their track assignments are systematically altered in order to make space for the current net being routed. In [9] the authors have developed a hop-based complete detailed router ROAD-HOP that uses the Bump & Refit (B & R) approach based on generating a minimum spanning tree (MST) from the complete pin-to-pin graph of each net to route a FPGA circuit. The FPGA routing tutorial [10] has a comparison of different FPGA routing techniques.…”