An effective design technique to reduce leakage power

Raj, Nikhil; Lorenzo, Rohit

doi:10.1109/sceecs.2012.6184722

Cited by 2 publications

(5 citation statements)

References 11 publications

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“…In CMOS VLSI circuits, power dissipation is basically due to the three important and major components: dynamic, static and short circuit. The switching activity is given by [8].…”

Section: Fig 1: Design Parametersmentioning

confidence: 99%

“…Due to the growing demand of battery operated devices, the power consumption has become a vital and major problem of integrated circuit designer. Scaling has result exponential increase in the leakage current [8]. The subthreshold leakage current I leakage can be given as…”

Section: Fig 1: Design Parametersmentioning

confidence: 99%

“…High threshold which are slow and have low sub threshold leakage current. The propagation delay is given by [8] …”

Section: Fig 1: Design Parametersmentioning

confidence: 99%

“…ITRS reported that leakage power consumption may come to dominate total chip power consumption as technology feature size shrinks [6,8]. It can observe be that static consumption tends to increase over the year as dynamic power consumption [11].…”

Section: Fig 1: Design Parametersmentioning

confidence: 99%

“…The voltage between drain and source also decreased since the intermediate node has a voltage above the ground resulting reduction in DIBL affect and hence effective saving of leakage power. For turned off the single transistor, leakage current Isub0 can be expressed as follows [3,8]:…”

Section: Fig 6: Circuit Schematic Of Forced Stack Technique [6]mentioning

confidence: 99%

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Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits

Aswale¹,

Chopade²

2013

IJCA

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Scaling of transistor features sizes has improves performance, increase transistor density and reduces the power consumption. A chip's maximum power consumption depends on its technology as well as its implementation. As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. As the threshold voltage is reduced due to scaling, it leads to increase in sub threshold leakage current and hence increase in static power dissipation. This paper presents performance analysis of inverter using conventional CMOS, stack and dual threshold transistor stacking, sleepy stack, sleepy keeper technique etc. The performance analyses of inverter were analyzed in 90nm technology using Virtuoso software (cadence). In order to reduce the static power dissipation, one has to sacrifice circuit performance and area. This paper presents the comparative study of all the approaches. The sleepy stack and variable body biasing approach shows improved results in terms of static power. General TermsLow power design, leakage power

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“…In CMOS VLSI circuits, power dissipation is basically due to the three important and major components: dynamic, static and short circuit. The switching activity is given by [8].…”

Section: Fig 1: Design Parametersmentioning

confidence: 99%

Section: Fig 1: Design Parametersmentioning

confidence: 99%

“…High threshold which are slow and have low sub threshold leakage current. The propagation delay is given by [8] …”

Section: Fig 1: Design Parametersmentioning

confidence: 99%

Section: Fig 1: Design Parametersmentioning

confidence: 99%

Section: Fig 6: Circuit Schematic Of Forced Stack Technique [6]mentioning

confidence: 99%

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