An Effective Approach for Thermal Performance Analysis of 3-D Integrated Circuits With Through-Silicon Vias

Chai, Jingrui; Dong, Gang; Yang, Yintang

doi:10.1109/tcpmt.2019.2893323

Cited by 24 publications

(5 citation statements)

References 24 publications

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“…They studied effective thermal conductivity and temperature variations with different pitches of PDN and TSVs in a 3-D IC stack. The influence of TCN layers on heat conduction introduced the following equations (5) and 6, ∆ = .…”

Section: Methodsmentioning

confidence: 99%

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Design and Introduction of Thermal Collection Network (TCN) for the Thermal Management in 3-D IC Structures

Patil

Suma

2021

Preprint

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Power in Watts of the chip, per unit area is growing exponentially in the electronic industry. At the same time, thermal problems becoming side effects of huge power consumption. Continuous efforts are getting made to remove the thermal problems of electronic packaging and systems. Thermal problems if not alleviated or suppressed, will lead the dielectric breakdown, electromigration, material creep, thermal cycling, chemical reactions, board warpage, performance drift, indirect heating, and many more problems. Likewise, a dedicated Power Delivery/distribution Network (PDN), can deliver the power to the chip base, this paper has introduced a new methodology of a dedicated Thermal Collection Network (TCN) in the same Back End Of Line (BEOL) area of the System in Package (SiP), System on Chip (SOC) and any other power-consuming chips. Adding a Thermal Through Silicon Via (TTSV) is another advantage in it. Using such an apparatus or methodology connected to TTSV will quickly pump-up the thermal energy to the heat-sink-fan assembly. Hence, preempting of heat from its sources can manage the thermal problems inside the chips or 3-D IC structures. The methodology uses the same copper metal stripes inside the Inter-Layer/Level-Dielectric (ILD), which will not lead to any extra copper to introduce more Coefficient of Thermal Efficiency (CTE) mismatch problems. It would be considered as one among the other metal stripes. The experimental results using the Finite Element Method (FEM) tool shown that 32% heat suction occurs in the TCNs, in monolithic ICs, and 11% in 3-D IC structures, compared to without such an approach. The junction temperature remained at 35%, with and without such an approach, in 3-D IC structures. This might lead to a new methodology for designing electronic chips and 3-D IC structures, in the future.

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Section: Methodsmentioning

confidence: 99%

“…This has helped to make the presented proposal, on how to design TCNs. Jingrui Chai, et al [5], studied an effective approach of thermal performance in a sacked IC system. Also studied the thermal conductivity in comparison with various publications.…”

Section: Introductionmentioning

confidence: 99%

Design and Introduction of Thermal Collection Network (TCN) for the Thermal Management in 3-D IC Structures

Patil

Suma

2021

Preprint

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“…Therefore, limited by the technical and economic difficulties in 3D-IC size scaling technology, the method of optimizing TTSV placement becomes particularly valuable [15]. In [16], an efficient 3-D multilevel routing approach was proposed, which included a novel TTSV planning method.…”

Section: Introductionmentioning

confidence: 99%

Optimized method for thermal through silicon via placement with non-uniform heat sources in 3-D-IC

Ding

Zhang

2023

THERM SCI

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In the past few years, thermal through silicon via (TTSV) has been experimentally investigated as an effective heat dissipation path. Although a lot of heat dissipation-related issues have been solved in three-dimensional integrated circuit (3D-IC), there are neglections in TTSV placement with non-uniform heat sources so far. In this study, a unique optimization is proposed to locate TTSV while effectively alleviating hot spots in 3D-IC. The thermal dissipation of non-uniform heat sources are studied using the finite element method. The simulation results show that the minimum temperature is reduced by 2.1% compared with peak temperature in the single-layer chip, and by 1.9% in the three-layer chip.

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“…This has sparked an interest in finding alternative ways to reap the benefits of vertical scaling using advanced packaging technologies utilizing 2.5D and 3D integration. Through-silicon-vias (TSVs) are the major building blocks upon which 3D integration relies upon, as the TSVs, acting as vertical interconnections, essentially route the signals and power through the various layers of the stacked integrated circuit (IC) [4]. In addition to ensuring a higher density of transistors per unit area, the vertical stacking of the chips using TSVs in a 3D IC also results in a significant reduction in the critical wire lengths when compared to the conventional 2D packaging technology.…”

Section: Introductionmentioning

confidence: 99%

Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs

Yadav¹,

Chauhan²,

Chawla³

et al. 2022

Semicond. Sci. Technol.

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In order to keep up with scaling trends, significant efforts are being undertaken in the direction of vertical stacking of integrated circuits. With advancements in packaging technology, chips are being stacked atop each other using through-silicon-vias (TSVs). The fabrication process for TSVs on a silicon substrate for these 3D integrated circuits (ICs) introduces mechanical stresses that in turn affect the electrical parameters of the surrounding transistors depending on their orientation and distance from the TSV. This introduces significant variability in key performance metrics, especially when the devices operate at lower than nominal supply voltages. In this work, a complete methodology is developed to predict the impact on the delay of a buffer chain designed using Fin Field-Effect Transistors (FinFETs) around the TSV. First, an analytical model is developed to predict the normal stress components in the silicon wafer due to the TSV, which is subsequently converted in a layout-dependent model for variations in key device-level parameters. Subsequently, a modified logical effort-based model is proposed to predict the delay of a buffer chain designed around the TSV.

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An Effective Approach for Thermal Performance Analysis of 3-D Integrated Circuits With Through-Silicon Vias

Cited by 24 publications

References 24 publications

Design and Introduction of Thermal Collection Network (TCN) for the Thermal Management in 3-D IC Structures

Design and Introduction of Thermal Collection Network (TCN) for the Thermal Management in 3-D IC Structures

Optimized method for thermal through silicon via placement with non-uniform heat sources in 3-D-IC

Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs

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