In order to keep up with scaling trends, significant efforts are being undertaken in the direction of vertical stacking of integrated circuits. With advancements in packaging technology, chips are being stacked atop each other using through-silicon-vias (TSVs). The fabrication process for TSVs on a silicon substrate for these 3D integrated circuits (ICs) introduces mechanical stresses that in turn affect the electrical parameters of the surrounding transistors depending on their orientation and distance from the TSV. This introduces significant variability in key performance metrics, especially when the devices operate at lower than nominal supply voltages. In this work, a complete methodology is developed to predict the impact on the delay of a buffer chain designed using Fin Field-Effect Transistors (FinFETs) around the TSV. First, an analytical model is developed to predict the normal stress components in the silicon wafer due to the TSV, which is subsequently converted in a layout-dependent model for variations in key device-level parameters. Subsequently, a modified logical effort-based model is proposed to predict the delay of a buffer chain designed around the TSV.
Several ultra-low power applications, that do not require high performance, can benefit from operation at the lowest possible supply voltage. Scaling of supply voltage is an effective method to reduce the energy consumption in digital circuits. The fundamental limit for supply voltage has been established as 36 mV for planar complementary metal oxide semiconductor (CMOS) circuits based on Shannon's channel capacity theorem. Owing to its near ideal sub-threshold characteristics, fin field effect transistor (FinFET) devices are a better fit for ultra-low voltage applications than planar devices. In this work, the fundamental limit on supply voltage for FinFET based logic circuits has been established for the first time. This theoretical limit is found to be significantly lower than the limit for planar CMOS circuits. The effect of variation of temperature and device design parameters on this fundamental limit is also explored. The analysis is extended to other logic gates such as NAND gate. Since the operation of a FinFET device in the ultra-low voltage domain is quite different from its planar counterpart, a novel physics based, semi-empirical current equation valid for supply voltage below 100 mV has been proposed for a FinFET device to calculate this fundamental limit. Such a current model is of great importance to a circuit designer because of the ease it offers for the back of the envelope calculations. The logic gates operating in this regime are then analyzed using this proposed model.
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