An EDA-Friendly Protection Scheme against Side-Channel Attacks

Abstract

Abstract-This paper introduces a generic and automated methodology to protect hardware designs from side-channel attacks in a manner that is fully compatible with commercial standard cell design flows. The paper describes a tool that artificially adds jitter to the clocks of the sequential elements of a cryptographic unit, which increases the non-determinism of signal timing, thereby making the physical device more difficult to attack. Timing constraints are then specified to commercial EDA tools, which restore the circuit functionality and efficiency while preserving the introduced randomness. The protection scheme is applied to an AES-128 hardware implementation that is synthesized using both ASIC and FPGA design flows.

Experiments on two clock countermeasures against power analysis attacks

“…So, during the coding of a block-data, the clock signal is stable, but every encoding run is slightly time shifted compared to the non countermeasured case. This differs from the implementation described in [6], in which the phase shift occurs every clock cycle. This change, compared to the implementation described in [6], has been required due to timing issues found in the synthesis of the particular AES encoder used in the experiments.…”

“…This differs from the implementation described in [6], in which the phase shift occurs every clock cycle. This change, compared to the implementation described in [6], has been required due to timing issues found in the synthesis of the particular AES encoder used in the experiments. So, the countermeasure actually implemented doesn't is exactly the same, but it can be considered as a variant.…”

“…2. According to Bayrak et al in [6], there is no need that all the delayers introduce the same time delay length. In the experiment setup used for the experiment described in this paper, the delay chain is composed of 16 delayers, whose outputs are selected via a 16-input multiplexer, so the control bus is 4-bit wide.…”

“…Significant cons are related to analysis/design/implementation complexity and/or feasibility by means standard cells. Both countermeasures analyzed in this paper exploit, in two different ways, a technique known as clock randomization [5], [6]. This technique, which can be integrated at low cost in the standard design flow, aims at randomizing the instants in time where the sensitive information is leaked through power consumption so increasing the complexity of an attack based on power analysis.…”

Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis Attacks

“…However, none of these works considered the impact of side-channel attacks (SCAs) to the systems. An automated protection technique for embedded cryptographic hardware was proposed in [13] to withstand SCAs. But the potential real-time requirements to the device was not mentioned.…”