An easy approach to formal verification

Abstract

Formal Verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds Formal Verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.

Behaviour Driven Development for Hardware Design

“…The authors of Ref. [33] use a FSM notation to add formal verification to the verification process with little to no knowledge of formal methods. This work also eases the use of formal verification by reducing the new training to a minimum by using natural language to approach formal verification step by step.…”