An early-completion-detecting ALU for a 1 GHz 64 b datapath

Kondo, Y.; Ikumi, N.; Ueno, K.; Mori, J.; Hirano, M.

doi:10.1109/isscc.1997.585466

Cited by 4 publications

(14 citation statements)

References 6 publications

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“…However, it is possible to reduce the count if circuits A and B share circuitry. Figure 3 shows an example of VLP applied to an ALU [10]. There are two kinds of circuits.…”

Section: Vlp Techniquementioning

confidence: 99%

“…Circuit A in Fig. 3 is designed so that no carry propagation over 16 bits is considered [10]. If the carry propagation for an operation is less than 16 bits, circuit A consisting of ALU parts I and III supplies its correct result, and most of the operations are included in this case.…”

Section: Vlp Techniquementioning

confidence: 99%

“…Kondo's group [10] proposed the VLP structure for integer ALUs. Using properly two kinds of circuits according to the longest path of the circuits for each operation, the effective execution latency can be almost always made to be one cycle, while the processor cycle time reaches 1 GHz.…”

Section: Related Workmentioning

confidence: 99%

“…This section proposes two solutions. Figure 2 shows the concept of the VLP [10]. A function can be implemented by several kinds of circuits whose design policies differ from each other.…”

Section: Variable Latency Pipeline Structurementioning

confidence: 99%

“…This combination of two kinds of circuits makes possible high-speed, short-latency execution for most of the operations. Kondo and colleagues evaluated the usefulness of VLP on a platform of an in-order execution scalar processor and found a 30% performance improvement [10], but the improvement is not clear for instructionlevel parallel (ILP) processors. Thus, in this paper, we will apply VLP to ILP processors [17] and will evaluate its usefulness based on detailed simulations.…”

Section: Introductionmentioning

confidence: 99%

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Combining variable latency pipeline with instruction reuse for execution latency reduction

Sato

Arita

2003

Systems & Computers in Japan

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SUMMARYOperand bypass logic is likely to be one of the critical structures for future microprocessors to achieve high clock speed. The logic delay causes the execution time budget to be reduced significantly, so that the execution stage is divided into several stages. The variable latency pipeline (VLP) structure has the advantages of pipelining and pseudo-asynchronous design. According to the source operands delivered to arithmetic units, VLP changes execution latency and thus achieves both high speed and low latency for most operands. In this paper we evaluate VLP with dynamically scheduled superscalar processors, using a cycle-by-cycle simulator. Our experimental results show that VLP successfully reduces the effective execution time, and thus relaxes the constraints on the operand bypass logic. We also evaluate the instruction reuse technique in order to support VLP.

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“…However, it is possible to reduce the count if circuits A and B share circuitry. Figure 3 shows an example of VLP applied to an ALU [10]. There are two kinds of circuits.…”

Section: Vlp Techniquementioning

confidence: 99%

Section: Vlp Techniquementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…This section proposes two solutions. Figure 2 shows the concept of the VLP [10]. A function can be implemented by several kinds of circuits whose design policies differ from each other.…”

Section: Variable Latency Pipeline Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Combining variable latency pipeline with instruction reuse for execution latency reduction

Sato

Arita

2003

Systems & Computers in Japan

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Design of synchronous and asynchronous variable-latency pipelined multipliers

Olivieri

2001

IEEE Trans. VLSI Syst.

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This paper presents a novel variable-latency multiplier architecture, suitable for implementation as a self-timed multiplier core or as a fully synchronous multicycle multiplier core. The architecture combines a second-order Booth algorithm with a split carry save array pipelined organization, incorporating multiple row skipping and completion-predicting carry-select final adder. The paper reports the architecture and logic design, CMOS circuit design and performance evaluation. In 0.35 μm CMOS, the expected sustainable cycle time for a 32-bit synchronous implementation is 2.25 ns. Instruction level simulations estimate 54% single-cycle and 46% two-cycle operations in SPEC95 execution. Using the same CMOS process, the 32-bit asynchronous implementation is expected to reach an average 1.76 ns throughput and 3.48 ns latency in SPEC95 execution

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Elastic Circuits

Carmona

Cortadella

Kishinevsky

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous design. Elasticity can be implemented both synchronously and asynchronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques. Thus, choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.

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An early-completion-detecting ALU for a 1 GHz 64 b datapath

Cited by 4 publications

References 6 publications

Combining variable latency pipeline with instruction reuse for execution latency reduction

Combining variable latency pipeline with instruction reuse for execution latency reduction

Design of synchronous and asynchronous variable-latency pipelined multipliers

Elastic Circuits

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