An automated design flow for 3d microarchitecture evaluation

Abstract

-Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact on overall system performance is still poorly understood due to the lack of tools and systematic flows to evaluate 3D microarchitectural designs. The contribution of this paper is the development of MEVA-3D, an automated physical design and architecture performance estimation flow for 3D architectural evaluation which includes 3D floorplanning, routing, interconnect pipelining and automated thermal via insertion, and associated die size, performance, and thermal modeling capabilities. We apply this flow to a simple, out-of-order superscalar microprocessor to evaluate the performance and thermal behavior in 2D and 3D designs, and demonstrate the value of MEVA-3D in providing quantitative evaluation results to guide 3D architecture designs. In particular, we show that it is feasible to manage thermal challenges with a combination of thermal vias and double-sided heat sinks, and report modest system performance gains in 3D designs for these simple test examples.

Multi-objective optimization and multi-criteria decision aid applied to the design of 3D-stacked integrated circuits

“…Since this is one of the most critical issues of 3D-SICs, this topic is actually a research field in itself with several developments of thermal-aware partitioners/floorplanners. One can cite the works in [26,27,83].…”

“…However, to the best of our knowledge, few 3D dedicated software currently exist. One can nevertheless cite the works in [26][27][28][29]. Most of other tools are mainly developed for and owned by particular manufacturers.…”

“…Automated design flow for 3D microarchitecture evaluation by Cong et al An automated design flow for 3D microarchitecture evaluation has been proposed by Cong et al [27]. They propose an evaluation flow for performance assessment and thermal management.…”

Fine grain 3D integration for microarchitecture design through cube packing exploration

“…However, these models are limited to folding blocks by wordlines or bitlines, and they do not explore further improvement from techniques such as port partitioning, which we shall discuss in Section 3. Other studies [4,28,22] same 2D floorplan to multiple layers, which in turn causes heating problems due to vertical stacking of hotspots. None of the previous studies explore the overall performance impact of using combination of 2D and 3D implementations of different components in the same design.…”

“…An extensive amount of research has demonstrated the latency reduction through additional device layers [1,2,3,4,30], however most prior art on 3D [4,5,6] is restricted to stacking traditional 2D dies. Such stacking offers significant reduction in inter-block latency, whereas it does little to help intra-block wire latency.…”