An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates

Ozdag, Recep O.; Beerel, Peter A.

doi:10.1109/tvlsi.2006.884049

Cited by 21 publications

(8 citation statements)

References 16 publications

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“…Most asynchronous design techniques such as Delay Insensitive (DI), Quasi Delay Insensitive (QDI), speed independent, scalable delay insensitive, bounded delay, and relative timing [ 3 ] require some timing assumption or constraints on the wires and components to ensure correct operation. Among the entire timing assumption models, the most commonly used template is the Caltech's QDI templates [ 4 ]. QDI is the practical approximation to Delay Insensitive design.…”

Section: Motivation For the Proposed Workmentioning

confidence: 99%

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Devi¹,

Palaniappan²

2015

The Scientific World Journal

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Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

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Section: Motivation For the Proposed Workmentioning

confidence: 99%

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Devi¹,

Palaniappan²

2015

The Scientific World Journal

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“…As a result, the state of the input buffer is a DTMC. It is assumed that the Fano decoder can execute one iteration per clock cycle which is feasible according to [22], so T s (n) is measured in clock cycles/codeword. The simulated distribution of T s will be used in the following analysis since its closed form expression is intractable.…”

Section: Dtmc Based Modeling On Single Ufa/bfamentioning

confidence: 99%

Low-complexity high-throughput decoding architecture for convolutional codes

Morris

Woodward

et al. 2012

J Wireless Com Network

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Sequential decoding can achieve a very low computational complexity and short decoding delay when the signalto-noise ratio (SNR) is relatively high. In this article, a low-complexity high-throughput decoding architecture based on a sequential decoding algorithm is proposed for convolutional codes. Parallel Fano decoders are scheduled to the codewords in parallel input buffers according to buffer occupancy, so that the processing capabilities of the Fano decoders can be fully utilized, resulting in high decoding throughput. A discrete time Markov chain (DTMC) model is proposed to analyze the decoding architecture. The relationship between the input data rate, the clock speed of the decoder and the input buffer size can be easily established via the DTMC model. Different scheduling schemes and decoding modes are proposed and compared. The novel high-throughput decoding architecture is shown to incur 3-10% of the computational complexity of Viterbi decoding at a relatively high SNR.

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“…All the strategies above are synchronous methods, but asynchronous design is usually known as a powerful low power strategy because asynchronous computational blocks can be designed to consume energy only when and where needed [12]. Asynchronous strategies have been applied to so many low power designs [13,14,15,16,17,18,19,20,21,22,23,24,25,26,27]. Several classic asynchronous low-power designs are briefly introduced in the following text.…”

Section: Introductionmentioning

confidence: 99%

Design of low-power low-area asynchronous iterative multiplier

You

Hei

Jia

et al. 2019

IEICE Electron. Express

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In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.

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An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates

Cited by 21 publications

References 16 publications

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Low-complexity high-throughput decoding architecture for convolutional codes

Design of low-power low-area asynchronous iterative multiplier

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