An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems

Turko, Timothé; Uhring, Wilfried; Dadouche, Foudil; Fesquet, Laurent

doi:10.1109/icecs.2018.8618023

Cited by 6 publications

(4 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An arbiter is used to determine the sequence of granting access to the shared resources when multiple input ports try to access the same output port. Different types of arbitration scheme available are round robin, lottery, token ring [24], and fixed priority [30]. Among all, round robin token scheme is the standard scheme which is used in Network on Chip for bus arbitration.…”

Section: Fig 1 -Basic Noc Architecturementioning

confidence: 99%

See 1 more Smart Citation

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Singh

Ravindra²,

Naik

2022

IJIE

View full text Add to dashboard Cite

Network-on-chip (NoC) provides solution to overcome the complications of the on-chip interconnect architecture in multi-core systems. It mainly consists of router, links and network interface. An essential component of on-chip router is an arbiter that significantly impacts the performance of the router. The arbiter should provide fast and fair arbitration when it is placed in Critical Path Delay (CPD) systems. The main aim of this research work is to design a novel arbiter for an effective network scheduler in complex real time applications. At the same time resource allocation and power consumption should be very low. Previously, a novel gate level Ping Lock Arbiter (PLA) is designed to overcome the limited fair arbitration in Improved Ping Pong Arbiter (IPPA) with less delay. But the chip size and power consumption are very high. To overcome this problem, an Effective Gate Diffusion Input (EGDI) logic-based CMOS scheme is used to design a novel Compact Ping Lock Arbiter (CPLA). The proposed CPLA is compared with the existing PLA based on static CMOS scheme. The comparison between the conventional and proposed arbiter is carried out to analyze the area, delay and power by using Tanner Tool 14.1 with 250nm and 45nm technology. The proposed CPLA is suitable for compact and smart applications with glitch free and fair arbitration. The proposed CPLA presents 41.2% reduction in total area consumption. It also provides 47.12% average Area and Power Product (APP) reduction when compared to the existing 4-bit PLA. Similarly, the proposed 8-bit CPLA shows 49.48% average APP product shrinkage when compared to conventional 8-bit PLA. For low power and area constraint applications, the proposed CPLA with EGDI is best in comparison to the static CMOS based ping lock round robin arbiter. Therefore, the results demonstrate that the proposed CPLA achieves low power and consumes less area than the existing ping lock arbiter.

show abstract

Section: Fig 1 -Basic Noc Architecturementioning

confidence: 99%

“…A high throughput arbiter based on fixed priority mechanism for applications related to Time Correlated Single Photon Counting system was presented in [30]. The major drawback of this technique is starvation of certain input requestors with more requests leading to increased wait time to get access to the resources.…”

Section: Related Workmentioning

confidence: 99%

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Singh

Ravindra²,

Naik

2022

IJIE

View full text Add to dashboard Cite

show abstract

“…In this work, in order to avoid the speed limitation inherent to DPAs, we decided to design and use a fixed-priority tree which is presented in the following sections [22].…”

Section: Asynchronous Priority-based Arbiter Readout Systemmentioning

confidence: 99%

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout

Aguénounon

Razavinejad

Schell

et al. 2021

Sensors

Self Cite

View full text Add to dashboard Cite

The usage of single-photon avalanche diode arrays is becoming increasingly common in various domains such as medical imaging, automotive vision systems, and optical communications. Nowadays, thanks to the development of microelectronics technologies, the SPAD arrays designed for these applications has been drastically well-facilitated, allowing for the manufacturing of large matrices. However, there are growing challenges for the design of readout circuits with the needs of reducing their energy consumption (linked to the usage cost) and data rate. Indeed, the design of the readout circuit for the SPAD array is generally based on synchronous logic; the latter requires synchronization that may increase the dead time of the SPADs and clock trees management that are known to increase power consumption. With these limitations, the long-neglected asynchronous (clockless) logic proved to be a better alternative because of its ability to operate without a clock. In this paper, we presented the design of a 16-to-1 fixed-priority tree arbiter readout circuit for a SPAD array based on asynchronous logic principles. The design of this circuit was explained in detail and supported by simulation results. The manufactured chip was tested, and the experimental results showed that it is possible to record up to 333 million events per second; no reading errors were detected during the data extraction test.

show abstract

“…Due to the analog units, the MUTEX circuit cannot be synthesized by mainstream EDA tools, which increases the design difficulty and prolongs the design time [12,13,14]. Various of asynchronous arbiters consists of the MUTEX have been proposed [15,16,17,18,19,20,21,22,23,5,6,24]. [16] put forward a simple 2-channel arbiter which cannot deal with the metastability problem so they introduced an uncertain delay line between request and acknowledgement.…”

Section: Introductionmentioning

confidence: 99%

Design of low latency asynchronous arbiter based on standard cell library

Zeng

Zhang

Shang

2022

IEICE Electron. Express

View full text Add to dashboard Cite

In this paper, a low-latency asynchronous arbiter based on standard cell library was proposed. The circuit which was implemented based on standard cell library, could be synthesized by mainstream EDA tools and suitable for being part of large-scale digital designs. With the employment of parallel processing techniques, Quick Request Forward and Quick Acknowledgement Release, which were able to reduce the release time by shortening the long feedback delay, the proposed asynchronous arbiter could provide a low latency. Post-layout simulations showed that the cycle time of the proposed arbiter was 7.3-40% better than existing arbiters in terms of latency in a simple communication model and 35.26-81.84% better in a complex communication model. In addition, the advantage became distinct as N increased.

show abstract

An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems

Cited by 6 publications

References 10 publications

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Design and Analysis of a Novel Low Complexity and Low Power Ping Lock Arbiter by using EGDI based CMOS Technique

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout

Design of low latency asynchronous arbiter based on standard cell library

Contact Info

Product

Resources

About