Design of low latency asynchronous arbiter based on standard cell library

Abstract

In this paper, a low-latency asynchronous arbiter based on standard cell library was proposed. The circuit which was implemented based on standard cell library, could be synthesized by mainstream EDA tools and suitable for being part of large-scale digital designs. With the employment of parallel processing techniques, Quick Request Forward and Quick Acknowledgement Release, which were able to reduce the release time by shortening the long feedback delay, the proposed asynchronous arbiter could provide a low latency. Post-layout simulations showed that the cycle time of the proposed arbiter was 7.3-40% better than existing arbiters in terms of latency in a simple communication model and 35.26-81.84% better in a complex communication model. In addition, the advantage became distinct as N increased.

Standard cell library design for edge computing chips

“…The design process of the standard cell library, as shown in Figure 1, begins by understanding various aspects of the PDK process characteristics, such as the voltage-current characteristics of MOS transistors, current variation with channel, MOS transistor driving capability, etc., before circuit design [11]. The specifications for the standard cell library are then established based on design requirements.…”