2019 IEEE 10th Latin American Symposium on Circuits &Amp; Systems (LASCAS) 2019
DOI: 10.1109/lascas.2019.8667576
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An asymmetrical bulk-modified composite MOS transistor with enhanced linearity

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Cited by 2 publications
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“…1 and also in Fig. 2, showing the extended linear range and 'saturation' effects as described in [1], [2]. In Fig.…”
Section: Introductionsupporting
confidence: 53%
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“…1 and also in Fig. 2, showing the extended linear range and 'saturation' effects as described in [1], [2]. In Fig.…”
Section: Introductionsupporting
confidence: 53%
“…1 two transistors are connected as a MOS divider to bias the bulk of the selftransistors, defining the equivalent transistor Meq with its own Source (S), Gate (G), Drain (D) terminals; the equivalent bulk terminal is not defined for Meq. As pointed in [1], [2], Meq shows an enhanced linear region, where the best results are obtained when the aspect ratios (W/L)a of Ma and (W/L)b of Mb are very different (W/L)a >> (W/L)b. Depending on the transistors' sizes, the resulting composite structure is linear up to an equivalent saturation VSat_eq voltage of a few hundred mV like in Fig.…”
Section: Introductionmentioning
confidence: 64%
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