An ASIP instruction set optimization algorithm with functional module sharing constraint

Al-Omary, Alauddin; Nakata, T.; Honma, Y.; Imai, M.; Hikichi, Nobuyuki

doi:10.1109/iccad.1993.580109

Cited by 39 publications

(16 citation statements)

References 5 publications

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“…Instruction set selection is treated as a module selection or operation coupling problem in [14], [27], and [28]. ASIP instruction set optimization under functional unit sharing constraints is addressed in [29]. A hardware-software codesign approach for instruction set selection is proposed in [30].…”

Section: A Related Workmentioning

confidence: 99%

Custom-Instruction Synthesis for Extensible-Processor Platforms

Sun

Ravi²,

Raghunathan³

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Efficiency and flexibility are critical, but often conflicting, design goals in embedded system design. The recent emergence of extensible processors promises a favorable tradeoff between efficiency and flexibility, while keeping design turnaround times short. Current extensible processor design flows automate several tedious tasks, but typically require designers to manually select the parts of the program that are to be implemented as custom instructions. In this work, we describe an automatic methodology to select custom instructions to augment an extensible processor, in order to maximize its efficiency for a given application program. We demonstrate that the number of custom instruction candidates grows rapidly with program size, leading to a large design space, and that the quality (speedup) of custom instructions varies significantly across this space, motivating the need for the proposed flow. Our methodology features cost functions to guide the custom instruction selection process, as well as static and dynamic pruning techniques to eliminate inferior parts of the design space from consideration. Furthermore, we employ a two-stage process, wherein a limited number of promising instruction candidates are first short-listed using efficient selection criteria, and then evaluated in more detail through cycle-accurate instruction set simulation and synthesis of the corresponding hardware, to identify the custom instruction combinations that result in the highest program speedup or maximize speedup under a given area constraint. We have evaluated the proposed techniques using a state-of-the-art extensible processor platform, in the context of a commercial design flow. Experiments with several benchmark programs indicate that custom processors synthesized using automatic custom instruction selection can result in large improvements in performance (up to 5.4 , an average of 3.4 ), energy (up to 4.5 , an average of 3.2 ), and energy-delay products (up to 24.2 , an average of 12.6 ), while speeding up the design process significantly.

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Section: A Related Workmentioning

confidence: 99%

Custom-Instruction Synthesis for Extensible-Processor Platforms

Sun

Ravi²,

Raghunathan³

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…A unique opportunity to trade off the flexibility of generalpurpose processor cores against the performance of hard-wired logic is offered by applicationspecific instruction-set processors (ASIPs). The instruction set of an ASIP is dedicated towards a particular class of applications by compound instructions that speed up critical parts of the applications without compromising the flexibility of the processor in its application domain [ 1,12,13,19]. Due to the diversity of the application domains that ASIPs are specialized in, it demands greater attention during synthesis tool development [2,3,11,14].…”

Section: Introductionmentioning

confidence: 99%

System Level Modeling Methodology of Application Specific Instruction Set Processor (SIP) Using SystemC

Mukherji

Das²

1970

Daffodil Int Uni J Sci Technol

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“…The work in [8] handled the selection of hardware accelerators in an ASIP. However, the hardware accelerators were very simple ones such as a multiplier and a divider, thus it did not consider the interface problem and possible parallel execution.…”

Section: Introductionmentioning

confidence: 99%

Exploiting intellectual properties in ASIP designs for embedded DSP software

Choi

Lee

et al. 1999

Proceedings of the 36th Annual ACM/IEEE Design Automation Conference

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The growing requirements on the correct design of a highperformance system in a short time force us to use IP's in many designs. In this paper, we propose a new approach to select the optimal set of IP's and interfaces to make the application program meet the performance constraints in ASIP designs. The proposed approach selects IP's with considering interfaces and supports concurrent execution of parts of task in kernel as software code with others in IP's, while the previous state-of-the-art approaches do not consider IP's and interfaces simultaneously and cannot support the concurrent execution. The experimental results on real applications show that the proposed approach is effective in making application programs meet the performance constraints using IP's.

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An ASIP instruction set optimization algorithm with functional module sharing constraint

Cited by 39 publications

References 5 publications

Custom-Instruction Synthesis for Extensible-Processor Platforms

Custom-Instruction Synthesis for Extensible-Processor Platforms

System Level Modeling Methodology of Application Specific Instruction Set Processor (SIP) Using SystemC

Exploiting intellectual properties in ASIP designs for embedded DSP software

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