Application specific instructions play an important role in reducins the required code size and increasing pe@orm-ante. This paper describes a ne)v approach to generate application specific instructions for DSP applications. The proposed approach is based on a modl~ed subset-sum problem, and can support multi-cycle complex instructions as Jvell as sinsle cycle instructions,~vhile the previous state-of-the-art approaches can Senerate only the singlecycle instructions or can just select instructions from the @ed super-set of possible instructions. In addition, the proposed approach can also be applicable to the case that instructions are predefine. The expen.mental results on real applications sho~v that the proposed approach is effective in making the instructions meet the given constraints )+~ithout attachins special hard~vareaccelerators.
Abstract:We propose a novel dynamic host mutation (DHM) architecture based on moving target defense (MTD) that can actively cope with cyberattacks. The goal of the DHM is to break the cyber kill chain, expand the attack surface to increase the attacker's target analysis cost, and disrupt the attacker's fingerprinting to disable the server trace. We define the participating entities that share the MTD policy within the enterprise network or the critical infrastructure, and define functional modules of each entity for DHM enforcement. The threat model of this study is an insider threat of a type not considered in previous studies. We define an attack model considering an insider threat and propose a decoy injection mechanism to confuse the attacker. In addition, we analyze the security of the proposed structure and mechanism based on the security requirements and propose a trade-off considering security and availability.
As the complexity of high-performance microprocessor increases, functional veri cation becomes more and more difcult and RTL simulation emerges as the bottleneck of the design cycle. In this paper, we suggest C language-based design and veri cation methodology to enhance the simulation speed instead of the conventional HDL-based methodologies. RTL C modelStreC describes the cycle-based behaviors of synchronous circuits and is followed by model re ning and optimization using LifeTime AnalyzerLTA and Cleaner. The simulation speed of cycle-based C model makes it possible to test the RTL design with the real-world" application programs in the order-of-magnitude faster speed than the commercial event-driven simulators. Using the proposed functional veri cation methodology, HK486, an intel 80486 -compatible microprocessor was successfully designed and veri ed.
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