An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-Chip

Tabrizi, Nozar; Bagherzadeh, Nader

doi:10.1109/icasic.2005.1611246

Cited by 10 publications

(4 citation statements)

References 6 publications

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“…However, the detriments include large numbers of processing elements (PE), high latency and the need to re-sort a full set of data upon a single new insertion. Martinez et al reduced sorting network latency by introducing levels of pipelining [4], while Tabrizi et al introduced a tree-like structure to reduce the area and PE complexity [5]. Nevertheless, sorting networks in general can not efficiently handle progressive incoming data, and their large area complexity may hinder implementation [6].…”

Section: A Sorting Networkmentioning

confidence: 99%

A configurable high-throughput linear sorter system

Ortiz

Andrews

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel in order to increase throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Implementation of this system into a Field Programmable Gate Array (FPGA) results in a speedup of 68 compared to quicksort running in a MicroBlaze processor.

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Section: A Sorting Networkmentioning

confidence: 99%

A configurable high-throughput linear sorter system

Ortiz

Andrews

2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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“…They proposed a network that can sort any M input data that is smaller than N, which is the maximum number of data that the netwotk can sort. In their work [5] Tabrizi and Bagherzadeh use a different sorting scheme. Basically, they use a tree as a network implemented in an ASIC, where the leaves of the tree are the inputs and the main node is the output.…”

Section: Sorting Networkmentioning

confidence: 99%

A versatile linear insertion sorter based on an FIFO scheme

Perez-Andrade

Cumplido

Feregrino-Uribe

et al. 2009

Microelectronics Journal

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A linear sorter based on First In First Out (FIFO) scheme is presented. It is capable of discarding the oldest value, inserting the incoming data while keeping the values sorted in a single clock cycle. This type of sorter can be used as coprocessor or as module in specialized architectures for order statistics filtering. The architecture is composed of identical processing elements thus can be easily adapted to any length according to specific application needs. The use of compact identical processing elements results in a high performance yet small architecture. Results of implementing the architecture on a Field Programmable Gate Array (FPGA) are presented and compared against other reported hardware based sorters.

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“…However, the detriments include large numbers of processing elements (PE), high latency, and the need to resort a full set of data upon a single new insertion. Martínez et al reduced sorting network latency by introducing levels of pipelining [8], while Tabrizi and Bagherzadeh introduced a tree-like structure to reduce the area and PE complexity [9]. Nevertheless, sorting networks in general cannot efficiently handle progressive incoming data, and their large area and complexity may hinder implementation [10].…”

Section: Introductionmentioning

confidence: 99%

A Streaming High-Throughput Linear Sorter System with Contention Buffering

Ortiz

Andrews

2011

International Journal of Reconfigurable Computing

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Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks, systolic sorters, and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel to increase overall throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Contention for available linear sorters in the system is solved through the use of buffers that accumulate conflicting requests, dispatching them in bulk to reduce latency penalties. Implementation of this system into a field programmable gate array (FPGA) results in a speedup of 68 compared to a MicroBlaze processor running quicksort.

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An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-Chip

Cited by 10 publications

References 6 publications

A configurable high-throughput linear sorter system

A configurable high-throughput linear sorter system

A versatile linear insertion sorter based on an FIFO scheme

A Streaming High-Throughput Linear Sorter System with Contention Buffering

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