A versatile linear insertion sorter based on an FIFO scheme

Perez-Andrade, Roberto; Cumplido, René; Feregrino-Uribe, Claudia; Campo, Fernando Martin del

doi:10.1016/j.mejo.2009.08.006

Cited by 23 publications

(4 citation statements)

References 8 publications

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“…They can be used to replace the first stages of mergesort [6] as well as in other FPGA sorting approaches [17]. A simple small-scale sorter is the linear sorter [18], [19] and can be seen as a parallel version of insertion sort [20]. As shown in the example of figure 4, a new value is inserted in every cycle.…”

Section: Small-scale Sortersmentioning

confidence: 99%

An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics

Papaphilippou

Brooks

Luk

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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This work improves on the latest research about sorting acceleration on FPGAs. An efficient design is introduced for sorting data that fit on-chip, with the additional functionality to merge sorted sublists recursively, for an input of arbitrary length. While many-leaf mergers are conventionally single-rate, a novel technique in our approach is to use a parallel merge tree only for the latest stages of the merge tree, to enable bandwidth-adapted multi-rate many-leaf merge. Our open-source RTL generator produces sorting peripherals with customisable parallelism and data format. We evaluate our FPGA design as an 128-bit wide peripheral on an MPSoC platform, with a speedup of up to 49 times over the A53 core for sorting, and up to 27 times speedup for our specialized database analytics application.

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Section: Small-scale Sortersmentioning

confidence: 99%

An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics

Papaphilippou

Brooks

Luk

2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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“…Better approach would be to use a priority queue for determining both minimal and maximal value, however the deletion of an arbitrary element from the priority queue is a demanding task. A sort structure with FIFO capabilities [25] proved to be an efficient solution in extracting the extreme values. This structure, depicted in Figure 5, implements an insertion sort where each value is stored within a sort cell together with its retire count.…”

Section: Hardware Architecture Of Lidar Data Compressionmentioning

confidence: 99%

Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

Biasizzo

Novak

2013

Sensors

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Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load.

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“…This sorting unit consists of two input FIFO queues where the merge is implemented by presenting the data from the two input FIFOs to a comparator-multiplexer block [27]. The comparator-multiplexer block indicates which element is greater and that element is then written into the output FIFO.…”

Section: Related Workmentioning

confidence: 99%

Analysis of Hardware Sorting Units in Processor Design

Furlan

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Sorting is often computationally intensive and can cause the application in which it is used to run slowly. To date, the quickest software sorting implementations for an N element sorting problem runs at O(nlogn). Current techniques, beyond developing better algorithms, used to accelerate sorting include the use of multiple processors or moving the sorting operation to a GPU. The use of multiple processors or a GPU can lead to increased energy consumption and heat produced by the device as compared to a single-core GPU-less implementation. To address these problems, specialized instructions and hardware units can be added to the processors to accelerate the sorting operation directly. This thesis studies and records the performance implications from implementing a sorting accelerator into a modern RISC-V processor pipeline. This thesis also explores the additional energy and area costs of implementing such hardware units in the processor.

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A versatile linear insertion sorter based on an FIFO scheme

Cited by 23 publications

References 8 publications

An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics

An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics

Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

Analysis of Hardware Sorting Units in Processor Design

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