An array processor design methodology for hard real-time systems

Abstract

Many hard real-time systems need huge computing power and they are mostly designed by ad hoc methods. A m y pmcessors provide a viable means to achieve huge computing power and they can be designed systematically. This paper presenb 4 sysfemafic design methodology to design a m y processor based hard real-time systems. Introduct'lonReal-time systems must produce not only logically correct results, but also meet timing constraints. Depending on the types of timing constraints, real-time systems are divided into two groups: Hard real-time systems and Soft real-time systems [l], [2]. A soft real-time system must produce computations as fast as possible such that a statistically described response time is satisfied. In a hard real-time system, computations must be finished before a given deadline.Analogous to the status of VLSI design at its infancy, currently there is no scientific basis for hard real-time system design [2]. Though most state-of-the-art hard real-time systems have been designed by ad hoc methods, a scientific approach for hard real-time system design is esSential as verification of the ad hoc designs are costly and error prone. Due to huge processing power requirements, almost all hard real-time systems need a multiprocessing edvironment. According to r2], a multiprocessor hard real-time system must possess the following features: Homogeneity, Scalability, Survivability and Flexibility.Array processors consist of a set of modular processing elements (PES) with spatially local communication, which makes them homogeneous and scalable. Survivability and flexibility can be introduced in the array processor design as well. Furthermore, systematic. methods are used in array processor designing. These factors make array processor based hard real-time systems very attractive. The array processors 01'-erating with synchronous (asynchronous) communication are called systolic (wavefront) arrays. As the array processor contains modular PES, only design problems associated with regular or partially-regular dependence graphs are considered for array processor design.The rest of this paper is organized as follows. In Section 2, we briefly describe the widely used dependence graph approach and its limitations for real-time array processor design. In Section 3, our design methodology is presented. Finally, conclusions are drawn in Section 4. can be handled by these. Therefore, the current practice is to make the DG regular while the algorithm is written in single assignment form [8]. If the given problem is not associated with a regular DG, dummy operations can be added to get a regular DG. The DGs for large and complex problems are not regular in general and are very difficult to make regular by adding dummy operations. On the other hand, duminy nodes keep the PES in the array processor busy unnecessarily. This could prevent the ability to meet hard real-time deadlines. Dependence Graph Based Array Processor Design and its Limitations Structured Dependence Graph Based Array Processor DesignTo simplify the ...

An array processor design methodology for hard real-time systems

“…In the following subsections, we describe these design steps briefly. More details are given in [9].…”

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