An area reduced design of the Context-Adaptive Variable-Length encoder suitable for embedded systems

Albanese, Loredana Freda; Licciardo, Gian Domenico

doi:10.1109/isvc.2010.5656302

Cited by 12 publications

(4 citation statements)

References 5 publications

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“…Furthermore, VS applications usually require great amounts of memory; for this reason the amount of memory required to implement the proposed architecture does not represent an actual problem in most VS applications. In fact, due to the implementation of frame buffers [22] or partial data storage [23][24][25], in these designs usually the memory requirements are in the order of Mbits, making the additional memory required to store the coefficients negligible.…”

Section: Resultsmentioning

confidence: 99%

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

2017

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Exploiting the Bachet weight decomposition theorem, a new two-dimensional filter is designed. The filter can be adapted to different multimedia applications, but in this work it is specifically targeted to image processing applications. The method allows emulating standard 32 bit floating point multipliers using a chain of fixed point adders and a logic unit to manage the exponent, in order to obtain IEEE-754 compliant results. The proposed design allows more compact implementation of a floating point filtering architecture when a fixed set of coefficients and a fixed range of input values are used. The elaboration of the data proceeds in raster-scan order and is capable of directly processing the data coming from the acquisition source thanks to a careful organization of the memories, avoiding the implementation of frame buffers or any aligning circuitry. The proposed architecture shows state-of-the-art performances in terms of critical path delay, obtaining a critical path delay of 4.7 ns when implemented on a Xilinx Virtex 7 FPGA board

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Section: Resultsmentioning

confidence: 99%

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

2017

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“…This technique reported from [6] permitted the reduction in the memory cost area. Table II reports the pseudo-code describing the elimination procedure, which presents the advantage of a very simple implementation circuitry.…”

Section: ) Arithmetic Table Elimination Technique For Level Encodermentioning

confidence: 99%

“…An arithmetic manipulation of encoding levels was exploited in [6] to eliminate some of the large size of conventional VLC LUTs.…”

Section: Introductionmentioning

confidence: 99%

Real-Time H.264/AVC Entropy Encoder Hardware Architecture in Baseline Profile

Asma¹,

Dhahri²,

Zitouni³

2017

ijacsa

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Abstract-In this paper, we present a new hardware architecture of an entropy encoder for an H.264/AVC video encoder. The proposed design aims to employ a parallel module at a pre-encoding stage to reduce a critical path. Additionally, the arithmetic table elimination method is used to eliminate the memory cost. Besides, the reduction in the size of VLC tables offers area saving. This architecture is synthesized on an FPGA Virtex IV. The simulation results show that this design can operate up to 234 MHz, which allows processing a 4CIF video format in real time.

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“…This is particularly important in resource-constrained devices, where area and power savings must be taken into serious consideration, 2 . 3 Such effort has been exacerbated in recent years by the widespread adoption of computationally intensive Machine Learning (ML) methods 4 in various applications, including but not limited to medical imaging, [5][6][7] image and video enhancement, 8,9 image segmentation, 10 defect detection, 11,12 person re-identification, 13 and remote sensing. [14][15][16] Many of these applications rely on Convolutional Neural Networks (CNNs) and digital filters, which require the parallel processing of several convolutions 1,2,17 for which the use of dedicated Hardware (HW) accelerators appears to be the only viable solution to meet the throughput requirements.…”

Section: Introductionmentioning

confidence: 99%

Self-adapting reconfigurable multiply-accumulator for real-time image processing in embedded systems

Fasolino,

Vitolo,

Liguori

et al. 2024

Real-Time Processing of Image, Depth, and Video Information 2024

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Multiply-Accumulate (MAC) operation is widely used in various real-time image processing tasks, ranging from Convolutional Neural Networks to digital filtering, significantly impacting overall system performance. In this work the Self-Adapting Reconfigurable Multiply-Accumulate (SR-MAC) is proposed as a new instrument to find the optimal trade-off between operation throughput, power consumption and physical resources utilization in real-time image processing applications. Operations of the proposed system rely on the dynamic reconfiguration of the hardware resources on the basis of the current computational requirements. This is achieved by monitoring overflow and over-representation occurrences at each accumulation cycle, and properly considering the relevant portion of the accumulation result. A custom architecture of the proposed algorithm has been designed and implemented on an AMD Xilinx Artix-7 FPGA through a Verilog description and compared to the AMD Xilinx fixed-point macro (floating-point fused multiply-accumulate). The SR-MAC achieves reductions of 83% (82%), 79% (93%) and 87.2% (94%) in the number of LUTs, FFs, and the power dissipation, P dynN , respectively. The SR-MAC has also been used to replace arithmetic units in typical real-time image processing applications. In these cases, its employment has allowed the reduction up to 6% and 14% of FFs and P dynN , respectively, while increasing up to 14% the f M ax . These results highlight the significant performance enhancement achieved with respect to both single operators and entire systems, making SR-MAC an excellent design choice in real-time image processing applications.

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An area reduced design of the Context-Adaptive Variable-Length encoder suitable for embedded systems

Cited by 12 publications

References 5 publications

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

Real-Time H.264/AVC Entropy Encoder Hardware Architecture in Baseline Profile

Self-adapting reconfigurable multiply-accumulator for real-time image processing in embedded systems

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