An Area Efficient SEU-Tolerant Latch Design

Wang, H.-B.; Bi, Jinshun; Li, M.-L.; Chen, Li; Liu, R.; Li, Y.-Q.; He, A.-L.; Guo, Gang

doi:10.1109/tns.2014.2361514

Cited by 24 publications

(5 citation statements)

References 18 publications

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“…A "true" low dose rate effect means that the degradation at lower dose rate radiation is larger than that at higher dose rate radiation (to the same dose) with a room temperature anneal for the equivalent time and bias condition. 7 An ELDRS effect means that the degradation induced by the lower dose rate radiation is more severe than that induced by the higher dose rate radiation at the same total doses with the equivalent time of radiation and annealing. Fig.…”

Section: A Dose Rate Effects On Unbiased Ccds Induce Saturation Outpmentioning

confidence: 99%

“…4 Zujun Wang et al have examined the dark signal degradation of the linear or array CCDs dependence on dose rates, and the effect of biased versus unbiased condition during radiation exposure. [5][6][7] Though these articles have studied the dose rate effects on the CCDs, they mainly focus on the dose rate effects on the degradation of dark signal in the CCDs. Few dose rate effects on the degradation of V S in the CCDs have been reported.…”

Section: Introductionmentioning

confidence: 99%

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Dose rate effects on array CCDs exposed by Co-60 γ rays induce saturation output degradation and annealing tests

Wang

Chen

et al. 2015

AIP Advances

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The experimental tests of dose rate and annealing effects on array charge-coupled devices (CCDs) are presented. The saturation output voltage (VS) versus the total dose at the dose rates of 0.01, 0.1, 1.0, 10.0 and 50 rad(Si)/s are compared. Annealing tests are performed to eliminate the time-dependent effects. The VS degradation levels depend on the dose rates. The VS degradation mechanism induced by dose rate and annealing effects is analyzed. The VS at 20 krad(Si) with the dose rate of 0.03 rad(Si)/s are supplemented to assure the degradation curves between the dose rates of 0.1 and 0.01 rad(Si)/s. The CCDs are divided into two groups, with one group biased and the other unbiased during 60Co γ radiation. The VS degradation levels of the biased CCDs during radiation are more severe than that of the unbiased CCDs.

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Section: A Dose Rate Effects On Unbiased Ccds Induce Saturation Outpmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Dose rate effects on array CCDs exposed by Co-60 γ rays induce saturation output degradation and annealing tests

Wang

Chen

et al. 2015

AIP Advances

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“…Despite that, SEU induced errors are transient(correctible) rather than permanent, and hence called as soft errors. SEU effects have been identified as the utmost threat to electronic systems operating reliably in the future by the Semiconductor Industry Association Roadmap [8][9].…”

Section: Introductionmentioning

confidence: 99%

Modeling and Simulation of Low Power Single Event Upset-resilient SRAM cell

Pannu

Prakash

2022

Preprint

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Radiation induced soft errors impact memory circuits and their response gets transposed or disturbed which makes it crucial to protect the memory unit. Radiation-immune memory devices have extensive applications in space, biomedical, smart devices, and wearable devices. A radiation hardened by design circuit using Dual Interlocked Storage Cell (DICE) is implemented with varied transistor sizing to propose the design that has optimum performance and power dissipation. The design is tested for Single Event Upsets using the double exponential current model for current source of maximum amplitude 1 A. The proposed design is validated in Cadence 180nm CMOS technology node at ±10% of VDD = 1.8 V. The sensitivity of the circuit to process, voltage and temperature variations are shown with the help of Monte Carlo simulations. Various iterations performed during simulations make the proposed circuit suitable for use in critical applications.

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“…Moreover, with technology scaling, circuit nodal capacitances and supply voltage has been reduced radically, which makes static random access memory (SRAM) more vulnerable to SEU. For SEU tolerable design, two types of hardened cell Quatro-10T [4] and DICE [5], as memory or latch or flip-flop cell, are broadly studied owing to their good SEU immunes [4,5,6,7,8]. DICE majorly relies on the extra principle of dual node feedback control to make it fully immune against a single node upset.…”

Section: Introductionmentioning

confidence: 99%

A radiation harden enhanced Quatro (RHEQ) SRAM cell

Peng

Chen

Zhang

et al. 2017

IEICE Electron. Express

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This paper intends to present a novel radiation-hardened SRAM cell by using the PMOS transistors stacked (each PMOS is split into two same sizes) and changing the inner topological structure on basis of the Quatro-10T. Combined with layout-level optimization design, the 3-D TCAD mixed-mode simulation results show that the novel design has a great single event upset (SEU) immune. Simultaneously, it is found to be tolerant of partial single-event multiple-node upsets (SEMNUs) due to the charge sharing among off-PMOS transistors. In addition, compared with the Quatro-10T, our proposed structure exhibits larger static noise margin (SNM) as well as lower power consumption in 65 nm COMS technology.

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An Area Efficient SEU-Tolerant Latch Design

Cited by 24 publications

References 18 publications

Dose rate effects on array CCDs exposed by Co-60 γ rays induce saturation output degradation and annealing tests

Dose rate effects on array CCDs exposed by Co-60 γ rays induce saturation output degradation and annealing tests

Modeling and Simulation of Low Power Single Event Upset-resilient SRAM cell

A radiation harden enhanced Quatro (RHEQ) SRAM cell

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