An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

Morita, Yasuhiro; Fujiwara, Haruhiko; Noguchi, Hiroki; Iguchi, Yusuke; Nii, Koji; Kawaguchi, Hiroshi; Yoshimoto, Masahiko

doi:10.1109/vlsic.2007.4342741

Cited by 120 publications

(65 citation statements)

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“…In 0.18μm technology, length of the transistor is varied from 0.6 μm to 0.12 μm, because of the increase in the length, surface area as well as power consumption of the total circuit elements will be reduced. Fig.3 shows the complete layout of the 8T cell with 0.18μmTechnology [9]. …”

Section: T Sram Cell Layout Designmentioning

confidence: 99%

Temperature Oriented Design of SRAM cell using CMOS Technology

Rukkumani¹,

Devarajan²

2015

IJCA

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A set of components in a circuit which are called as modules or blocks are connected through interconnections called as 'wires'. Various computational techniques are used to calculate and minimize the area, power and speed. Single IC consists of number of Processing Elements (PE's), which works on various voltage ranges. Due to this the IC power consumption increases, thereby temperature of the chip also increases. The increased temperature in some parts is called as hotspots. The main goal of this paper is to focus on calculation of area, power and hotspot of SRAM memory circuit for 8T and 10T memory cell using Microwind.This may used to design of many complicated memory circuits for various temperature ranges. The Submicron Technology is widely used for designing any complex analog circuits.

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Section: T Sram Cell Layout Designmentioning

confidence: 99%

Temperature Oriented Design of SRAM cell using CMOS Technology

Rukkumani¹,

Devarajan²

2015

IJCA

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“…Double-ended 6T (6 transistors) SRAM cells have been widely deployed for high voltage operation. Numerous SRAM cell designs such as 8T [16], Schmitt-Trigger 10T (10T) [12], etc. target different voltage and robustness scenarios.…”

Section: Related Workmentioning

confidence: 99%

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Marić¹,

Abella²,

Valero³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 C) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips.This paper proposes a novel, hybrid-operation (high Vcc, ultralow Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.

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“…Consequently, VARIUS-NTV uses the 8-transistor cell of Figure 4(b) [8], [29]. This cell is easier to design reliably because it decouples the transistors used for reading (AX RD and N RD ) and those for writing (the rest).…”

Section: B Sram Cellmentioning

confidence: 99%

VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages

Karpuzcu

Kolluru

Kim

et al. 2012

IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2012)

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Abstract-Near-Threshold Computing (NTC), where the supply voltage is only slightly higher than the threshold voltage of transistors, is a promising approach to attain energy-efficient computing. Unfortunately, compared to the conventional SuperThreshold Computing (STC), NTC is more sensitive to process variations, which results in higher power consumption and lower frequencies than would otherwise be possible, and potentially a non-negligible fault rate.To help address variations at NTC at the architecture level, this paper presents the first microarchitectural model of process variations for NTC. The model, called VARIUS-NTV, extends the existing VARIUS variation model. Its key aspects include: (i) adopting a gate-delay model and an SRAM cell type that are tailored to NTC, (ii) modeling SRAM failure modes emerging at NTC, and (iii) accounting for the impact of leakage in SRAM models. We evaluate a simulated 11nm, 288-core tiled manycore at both NTC and STC. The results show higher frequency and power variations within the NTC chip. For example, the maximum difference in on-chip tile frequency is ≈2.3x at STC and ≈3.7x at NTC. We also validate our model against an experimental chip.

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An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

Cited by 120 publications

References 0 publications

Temperature Oriented Design of SRAM cell using CMOS Technology

Temperature Oriented Design of SRAM cell using CMOS Technology

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages

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