An Approach for Efficient Metastability Characterization of FPGAs through the Designer

Polzer, Thomas; Steininger, Andreas

doi:10.1109/async.2013.14

Cited by 20 publications

(12 citation statements)

References 25 publications

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“…Interestingly, the late transition detector circuits usually employed for obtaining the MTBU curve can be bene¯cially used here as well. 11 However, the interpretation of the readouts then di®ers in detail from the one applied for MTBU prediction: As already outlined, here we are not concerned with discriminating \proper" reaction times from \upsets"; we are just measuring the delay without a need for interpreting it. It is important to note here that the measurement principle applied in the detection circuit does not allow an absolute calibration of the delay, i.e., just the di®erence between delays for di®erent settings of ÁT can be determined.…”

Section: Determination Of the Relevant Parametersmentioning

confidence: 99%

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A Model for the Metastability Delay of Sequential Elements

Polzer

Steininger

2017

J CIRCUIT SYST COMP

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It is well known that every sequential element may become metastable when provided with marginal inputs, such as input transitions occurring too close or input voltage not reaching a de¯ned HI or LO level. In this case the sequential element requires extra time to decide which digital output level to¯nally present, which is perceived as an output delay. The amount of this delay depends on how close the element's state is to the balance point, at which the delay may, theoretically, become in¯nite. While metastability can be safely avoided within a closed timing domain, it cannot be completely ruled out at timing domain boundaries. Therefore it is important to quantify its e®ect. Traditionally this is done by means of a \mean time between upsets" (MTBU) which gives the expected interval between two metastable upsets. The latter is de¯ned as the event of latching the still undecided output of one sequential element by a subsequent one. However, such a de¯nition only makes sense in a time-safe environment like a synchronous design. In this paper we will extend the scope to so-called value-safe environments, in which a sequential element can safely¯nalize its decision, since the subsequent one waits for completion before capturing its output. Here metastability is not a matter of \failure" but a performance issue, and hence characterization by MTBU is not intuitive. Therefore we will put the focus on the delay aspect and derive a suitable model. This model extends existing approaches by also including the area of very weak metastability and thus providing complete coverage. We will show its validity through comparison with transistor-level simulation results for the most popular sequential elements in di®erent implementations, point out its relation to the traditional MTBU model parameters, namely and T 0 , and show how to use it for calculating the performance penalty in a value-safe environment.

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Section: Determination Of the Relevant Parametersmentioning

confidence: 99%

“…To calculate the excess delay, we subtract the nominal output delay from Eq. (11). The nominal output delay is de¯ned as the delay for an in¯nite large signal overlap:…”

Section: Estimating Performance Penaltymentioning

confidence: 99%

A Model for the Metastability Delay of Sequential Elements

Polzer

Steininger

2017

J CIRCUIT SYST COMP

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“…More speci¯cally, we use the circuit from Ref. 15 for detecting late transitions allowing a very detailed analysis of metastability behavior.…”

Section: Projections On the E®ect Of And And Or Gatingmentioning

confidence: 99%

On the Appropriate Handling of Metastable Voltages in FPGAs

Polzer

Najvirt

Beck

et al. 2015

J CIRCUIT SYST COMP

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The signi¯cant process, voltage and temperature (PVT) variations seen with modern technologies make strictly synchronous design ine±cient. Asynchronous design with its°exible timing is a promising alternative, but prototyping is di±cult on the available FPGA platforms which are clock centric and do not provide the required functional primitives like mutual exclusion or Muller C-elements. The solutions proposed in the literature so far work nicely in principle but cannot safely handle metastability issues that are inevitable even at some interfaces in asynchronous designs. In this paper, we propose reliable implementations of the fundamental function blocks required to safely convert potential intermediate voltage levels that result from metastability into late transitions that can be reliably handled in the asynchronous domain. These are high-and low-threshold bu®ers as well as a Schmitt-trigger. We give elaborate background analysis for the proposed circuits and also present the associated routing constraints to make the Schmitt-trigger circuit work properly in spite of the uncertain routing within FPGAs. Furthermore, we propose a procedure for an \in situ reliability assessment" of the speci¯c Schmitt-trigger element under consideration, which also applies to metastability containment with high-or low-threshold bu®ers only. Our proof of concept is based on experimental results for both Xilinx and Altera FPGA platforms.

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“…Two approach for characterizing the metastability in state elements: random approach and deterministic approach [7]. In the random approach, input signals (data and clock) for state elements are independent.…”

Section: Introductionmentioning

confidence: 99%

“…In deterministic approach, the inputs are concentrated on an interest region controllably. In [7], and [8], they applied the random approach to characterize the metastability for a Flip-Flop on an FPGA Virtex-4. Similarly, the work in [9] characterized the metastability of Flip-Flips on 65 nm CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

Measurements of metastability in MUTEX on an FPGA

Toan

Tung

Lee

2018

IEICE Electron. Express

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In this paper, we propose a new method for measuring metastability in the mutual exclusion element (MUTEX) implemented on a Field Programmable Gate Array (FPGA). Our method uses fine-grained phase shifts of a digital clock manager to trigger Flip-Flops to generate concurrent inputs for a MUTEX. By dynamically adjusting the phase shift between two clock signals, we can force the MUTEX into a metastable state. The benefit of our approach is that it is easier to force the MUTEX become metastable compared to the conventional approach using two un-correlated signals. The experiments have been performed on a Xilinx Spartan-6 (XC6SLX9-4TQG144C).

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An Approach for Efficient Metastability Characterization of FPGAs through the Designer

Cited by 20 publications

References 25 publications

A Model for the Metastability Delay of Sequential Elements

A Model for the Metastability Delay of Sequential Elements

On the Appropriate Handling of Metastable Voltages in FPGAs

Measurements of metastability in MUTEX on an FPGA

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