An Applicatin of Micro-Ball Wafer Bumping to Double Ball Bump for Flip Chip Interconnection

Tatsumi, Kohei; Yamamoto, Yasutaka; Iwata, Keiji; Hashino, Eiji; Ishikawa, Satoshi; Kohno, Takuo; Miyajima, F.; Nakazawa, Hiroyuki

doi:10.1109/ectc.2005.1441372

Cited by 4 publications

(2 citation statements)

References 5 publications

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“…These include evaporation [1], paste screening [3], electroplating [4], and the direct attach of preformed solder spheres. [5] However, not all of these C4 bumping technologies are extendable to fine-pitch applications for volume production at low cost. In addition, as the microelectronic packaging industry is moving to the "green" Pb-free solder as mandated by the European Union (EU) RoHS legislation, the high Sncontent solder has presented major challenges in meeting reliability requirements.…”

Section: Introductionmentioning

confidence: 99%

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Shih

Dang

Gruber

et al. 2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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Controlled Collapse Chip Connection -New Process (C4NP) technology is a novel solder bumping technology developed by IBM to address the limitations of existing bumping technologies. Through continuous improvements in processes, materials and defect control, C4NP technology has been successfully implemented at IBM in the manufacturing of all 300mm Pb-free solder bumped wafers. Both 200 µm and 150 µm pitch products have been qualified and are currently ramping up volume production.Extendibility of C4NP to 50 µm ultra-fine pitch microbump application has been successfully demonstrated with the existing C4NP manufacturing tools. Targeted applications for microbumps are three-dimensional (3D) chip integration and the conversion of memory wafers from wirebonding (WB) to C4 bumping. The metrology data on solder volume, bump height, defect and yield have been characterized by RVSI inspection. This paper reviews the C4NP processes from mold manufacturing, solder fill and solder transfer onto 300 mm wafers, along with defect and yield analysis. Reliability challenges as well as solutions in the development and qualification of flip chip Pb-free solder joint are also reviewed. In addition to a suitable under bump metallurgy (UBM), a robust lead-free solder alloy with precisely controlled composition and special alloy doping is needed to enhance performance and reliability.

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Section: Introductionmentioning

confidence: 99%

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Shih

Dang

Gruber

et al. 2008

2008 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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“…Since the introduction of the flip chip technology by IBM in the 1960s [12], various flip chip bumping technologies were reported, including Physical Vapor Deposition (PVD) [13][14][15], electroplating [16][17][18], liquid metal jetting [19], ball or stud bumping using conventional wire-bonding process [20,21], stencil printing [22], and micro-ball bumping [23][24][25]. Although the PVD methods, which include sputtering and evaporation, are proven and popular technologies, the uneconomical material consumption and large vacuum chamber result high cost.…”

Section: Introductionmentioning

confidence: 99%

Chip scale packaging with surface mountable solder ball terminals for microsensors

Lee¹,

Lee

et al. 2009

2009 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems

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This paper presents a simple and low-cost flip chip bumping method with vertical feedthroughs for MEMS WLCSP. The vertical feedthroughs are fabricated on glass wafer using sand-blasting, and these provide inherent aligning jig for microball arrangement. The experimental evaluations using MEMS accelerometer are also presented. The proposed method can be a more cost-effective solution by eliminating the conventional expensive and complex process including electroplating or ballaligning jig. The feasibility of WLCSP is experimentally demonstrated by testing the developed devices.

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Novel method to extract arrays of aligned carbon nanotube bundles from CNT film using solder ball grid arrays for higher performance device interconnects

Hildreth

Lin

Alvarez

et al. 2009

2009 59th Electronic Components and Technology Conference

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Carbon nanotubes (CNTs) are an attractive electrical interconnect material due to their excellent mechanical, electrical and thermal properties. Despite these advantages CNTs have not been widely adopted by industry primarily because of the difficulties associated with integrating CNTs into device electronics. In this paper we demonstrate that bundles of aligned CNTs can be extracted directly from a CNT film using solder ball grid arrays (BGA). The resulting CNT bundles adhere directly to the solder balls and show good vertical alignment. The affect of flux, CNT application displacement and solder ball phase (liquid or solid) on CNT bundle alignment and coverage area were examined. This simple process could be used to mechanically decouple the BGA from the substrate, reducing solder ball fatigue due to thermal cycling and increasing device reliability.

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An Applicatin of Micro-Ball Wafer Bumping to Double Ball Bump for Flip Chip Interconnection

Cited by 4 publications

References 5 publications

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

C4NP for Pb-free solder wafer bumping and 3D fine-pitch applications

Chip scale packaging with surface mountable solder ball terminals for microsensors

Novel method to extract arrays of aligned carbon nanotube bundles from CNT film using solder ball grid arrays for higher performance device interconnects

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