An analytical retention model for SONOS nonvolatile memory devices in the excess electron state

Wang, Yu; White, M.H.

doi:10.1016/j.sse.2004.06.009

Cited by 135 publications

(83 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The time constant of T-B, τ T-E , and the time constant of τ T-E are written as [11]: (1) (2) where τ T-E is a time constant [13], [11] are the electron effective mass in the SiO 2 and Si 3 N 4 , respectively, here m 0 is the free electron mass. E T is the trap energy level referenced to the conduction band edge in the Si 3 N 4 (eV), q is the absolute electron charge, E B =1.05 eV [15] is the energy barrier height of electron tunneling (eV), h is Planck's constant, d TO is the thickness of the SiO 2 (nm), T is the absolute temperature (K), A is the temperature independent constant, k B is Boltzmann's constant, t is the retention time (s) and is the tunneling distance in the Si 3 N 4 measured from the SiO 2 /Si 3 N 4 interface as follows (nm):…”

Section: Resultsmentioning

confidence: 99%

“…Also, a reasonable nitride thickness range was obtained through electrical characteristic measurements. Four charge loss mechanisms [11,12] are involved in the data retention state for scaled CTF memory devices: trapped electrons tunnel from traps to the silicon conduction band (T-B), trapped electrons tunnel from traps to the Si/SiO 2 interface traps state (T-T), holes tunnel from the silicon valence band to nitride traps (B-T) and thermal excited trapped electrons from the traps to the nitride conduction band followed by tunneling through the tunnel oxide (T-E), as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

“…1. However, the T-B and T-E mechanisms are regarded as the two main electron loss mechanisms [11]. Therefore, in our case we only consider the T-B tunneling and T-E mechanisms.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

Tang¹,

Ma²,

Zhang³

et al. 2014

Transactions on Electrical and Electronic Materials

View full text Add to dashboard Cite

charge trap flash memory structures with various thicknesses of the Si 3 N 4 charge trapping layer were fabricated. According to the calculated and measured results, we depicted electron loss in a schematic diagram that illustrates how the trap to band tunneling and thermal excitation affects electrons loss behavior with the change of Si 3 N 4 thickness, temperature and trap energy levels. As a result, we deduce that Si 3 N 4 thicknesses of more than 6 or less than 4.3 nm give no contribution to improving memory performance.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

Tang¹,

Ma²,

Zhang³

et al. 2014

Transactions on Electrical and Electronic Materials

View full text Add to dashboard Cite

show abstract

“…However, today the scaling of standard planar flash structures having floating gate seems to face serious limitations, due to the loss of memory cell electrostatic integrity and the appearance of parasitic inter-coupling between adjacent cells in the arrays [1]. In addition, since the tunneling oxide thickness in floating gate memory devices is relatively thick to suppress the stress induced leakage current (SILC), the high voltages are required for the write and erase operations [2].…”

Section: Introductionmentioning

confidence: 99%

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

Lee¹,

Joe²,

Yun³

et al. 2012

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps (N IT ). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of N IT originated by the movement of hydrogen species (h * ) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the N IT generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated N IT .

show abstract

“…In this context, memories based on charge trapping layers, combined with high-k blocking oxides (as SANOS [1] and TANOS (TaN/Al2O3/SiN/SiO2/Si) [2] structures) are widely investigated for sub-32nm node generations. Several studies of TANOS-like structures have been presented, analyzing the retention mechanisms [3][4], proposing the optimization of the gate stack to improve the performances [5][6], or simulating the programming-erasingretention mechanisms [7]. Replacing SiO2 with a high-k material, as Al2O3, as top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer, during write and erase operations.…”

Section: Introductionmentioning

confidence: 99%

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

Bocquet

Molas

Perniola

et al. 2009

Solid-State Electronics

View full text Add to dashboard Cite

In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al2O3 bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/ HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed, focusing on their impact on memory performance and reliability. Then, a semi-analytical model is developed, which provides a good understanding of the physical mechanisms at the origin of program/erase characteristics.

show abstract

An analytical retention model for SONOS nonvolatile memory devices in the excess electron state

Cited by 135 publications

References 22 publications

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

Dependence of Electrons Loss Behavior on the Nitride Thickness and Temperature for Charge Trap Flash Memory Applications

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

Contact Info

Product

Resources

About