A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

Abstract

Abstract-The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps (N IT ). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of N IT originated by the movement of hydrogen species (h * ) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the N IT generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated N IT .

Memristively programmable transistors

“…This is achieved by using a relatively small read-voltage (within a read-margin) for the selected transistor and a relatively high CT voltage for the unselected transistors. In this case, the selected transistor shows a high ON/OFF drain-current ratio (typically in the order of 10 3 -10 6 ) [49][50][51]. In contrast, the drain-current of the unselected transistors only scales by a factor typically <10 and does not limit the drain-current of the selected transistor.…”

Three‐dimensional AND flash memory

“…In addition, a three-dimensional (3D) approach of stacking memory array was introduced to overcome problems of conventional 2D planar NAND technology [2,3]. The V-NAND flash technology can solve problems such as cell-to-cell interference and prohibitive patterning [4,5]. However, there are limitations on the number of stacked layers due to an inherent NAND string structure.…”