An Analytical Modeling and Simulation of Surrounding Gate TFET with an Impact of Dual Material Gate and Stacked Oxide for Low Power Applications

Abstract

In this paper, an analytical model for modified Surrounding Gate Tunnel FET with gate stack engineering and different gate metals has been developed. Further, considering the scaling advantageous of Gate stack engineering and high degree performance of dual material engineering, the both has been integrated into a novel structure known as Surrounding Gate (SG) Tunnel FET with stacked oxide SiO2/high-k and dual material (DM) has been proposed. The two dimensional (2D) potential at the surface and electric field mathematical models for the DMSG TFET are developed by solving 2D Poisson's equation with matching device boundary conditions. Based on the Kane's formula, mathematical expression for the band-to-band (BTB) tunneling generation rate is derived and then used to calculate the drain current. The impact on the proposed device performance due to the variation of different device parameters has also been studied. It has been found from the presented results that the ON current of the DMSG TFET with stack is 10-6A, OFF current is 10-13A and ON/OFF ratio is 107. The mathematical results have been verified using the simulated results obtained from TCAD, a 3-D device simulator from ATLAS.