An Analytical Model for Silicon-on-Insulator Reduced Surface Field Devices with Semi-Insulating Polycrystalline Silicon Shielding Layer

Ho, Chi-Hon; Liao, Chien-Nan; Chien, Feng-Tso; Tsai, Y.T.

doi:10.1143/jjap.47.5369

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…In recent years, silicon-on-insulator (SOI) is a promising technology for the power ICs because of its high output power, high breakdown voltage, low specific on-resistance, analog-digital compatibility, and low cost. [1][2][3] One of the main issues concerning the design of the SOI device is the trade-off between breakdown voltage (BV) and specific onresistance (R sp ). [4][5][6][7] To resolve this issue, many technologies have been proposed.…”

Section: Introductionmentioning

confidence: 99%

Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique

Yao

Guo

et al. 2015

Jpn. J. Appl. Phys.

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Recently, the variation of lateral thickness (VLT) technique has been proposed as an effective lateral voltage-sustaining technology. However, no analytical model has been reported for exploring the physical mechanism quantitatively. By solving the two-dimensional (2D) Poisson equation, an analytical model for a silicon-on-insulator (SOI) device with a VLT structure is proposed in this paper to optimize the surface potential and electric field distribution of the VLT SOI device. The lateral and vertical breakdown voltages are formulized to quantify the breakdown characteristic. The drift doping concentration range is derived to maximize the breakdown voltage. This model is used to investigate the electric field distribution and breakdown voltage of the VLT SOI device with various parameters. The validity of the proposed model is verified by the fair agreement between the analytical and numerical results.

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Section: Introductionmentioning

confidence: 99%

Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique

Yao

Guo

et al. 2015

Jpn. J. Appl. Phys.

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“…The performance of SOI device is affected by the substrate bias. For a power diode built by SOI technology, the influence of the substrate bias on the breakdown voltage is eliminated by inserting a semi-insulating polycrystalline silicon layer (SIPOS) [6]. But the SIPOS layer is not compatiable with the standard power IC technology, because the leakage current is increased by the SIPOS over silicon interface traps [7,8].…”

Section: Introductionmentioning

confidence: 99%

Optimum Design for Eliminating Back Gate Bias Effect of Silicon-oninsulator Lateral Double Diffused Metal-oxide-semiconductor Field Effect Transistor with Low Doping Buried Layer

Ho¹,

Chien²,

Liao³

et al. 2008

TOEEJ

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An optimum design with silicon-on-insulator (SOI) device structure was proposed to eliminate back gate bias effect of the lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOSFET) and to improve breakdown voltage. The SOI structure was characterized by low doping buried layer (LDBL) inserted between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter to affect the strong inversion condition in the back MOS capacitor of the new SOI diode. The optimum design of LDBL thickness for the SOI diode was 2.65 μm. Furthermore, the breakdown capability has been improved 11%.

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Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

Chien-Nan

Chien

et al. 2009

Chinese Phys. Lett.

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This work presents the optimal design of a silicon-on-insulator (SOI) diode structure to eliminate the back gate bias effect and to improve breakdown voltage. The SOI structure is characterized by inserting a silicon low doping buried layer (LDBL) between the silicon layer and the buried oxide layer. The LDBL thickness is a key parameter that affects the strong inversion condition of the back MOS capacitor of the new SOI diode. The optimal LDBL thickness in the SOI diode is 2.65 𝜇m. The LDBL shielding layer improved the breakdown voltage.

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An Analytical Model for Silicon-on-Insulator Reduced Surface Field Devices with Semi-Insulating Polycrystalline Silicon Shielding Layer

Cited by 3 publications

References 14 publications

Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique

Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique

Optimum Design for Eliminating Back Gate Bias Effect of Silicon-oninsulator Lateral Double Diffused Metal-oxide-semiconductor Field Effect Transistor with Low Doping Buried Layer

Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

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