An analytical method for evaluating Network-on-Chip performance

Foroutan,; Thonnart,; Hersemeule,; Jerraya,

doi:10.1109/date.2010.5457072

Cited by 26 publications

(25 citation statements)

References 11 publications

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“…But it does not consider the flow-control feedback mechanism, which is caused by the fullness of the input queue of the successive router. [5], based on the same assumption, uses numerical analysis and iterative computation to estimate performance. In contrast with them, flowcontrol feedback probability is one of the research focuses here.…”

Section: Previous Workmentioning

confidence: 99%

Model of Network-on-Chip routers and performance analysis

Zhang

Xiaoguo

Gan

et al. 2011

IEICE Electron. Express

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Abstract:This paper presents a generic analytical performance model of Network-on-Chip (NoC) router, which is further used to analyze the performance of a whole wormhole NoC. We focus on the analysis of various packet blocking-conditions at the router input-queues for a more accurate estimation of waiting time. Based on this estimation, some key performance metrics of NoC, such as the buffer utilization and packet transfer latency, are both computed. Compared with some previous model, it presents more accurate results: for buffer utilization ratio, the error is 6.30%; for packet transfer latency, it is about 5.98%. Keywords: Network-on-Chip, markov chain, performance analysis Classification: Integrated circuits

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Section: Previous Workmentioning

confidence: 99%

Model of Network-on-Chip routers and performance analysis

Zhang

Xiaoguo

Gan

et al. 2011

IEICE Electron. Express

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“…This work again assumes the Poisson arrivals for the flows. In [23] the authors proposed a probabilistic model to find the average buffer utilization of a flow accounting for the presence of other flows across all ports. The authors of [24] used an approach to minimize buffer demand by regulating traffic through a delayed release mechanism and hence achieving the goal of appropriate buffer sizing.…”

Section: Related Workmentioning

confidence: 99%

A Buffer‐Sizing Algorithm for Network‐on‐Chips with Multiple Voltage‐Frequency Islands

Kumar

Murali³

et al. 2012

Journal of Electrical and Computer Engineering

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Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.

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“…This multimedia application used for the evaluation of end-to-end latency for the methods proposed in [16] and [5]. We manually map the application into 4x4 2D mesh NoC with a single VC for all links.…”

Section: Evaluation Of Use Casesmentioning

confidence: 99%

“…Previous works have presented analysis methodologies for NoCs with a single-VC [2,5,15,16], a uniform (same for all links) number of VCs [19,10,9,13] and "infinite" number of VCs [6,12,1].…”

Section: Introductionmentioning

confidence: 99%

“…However, exiting analysis methodologies [2,5,15,16,19,10,9,13] are based on the assumption that NoCs are homogeneous. Figure 1 illustrates the delay evaluation of a heterogeneous NoC for two existing extreme analysis methodologies: single-VC [2,5,15,16] and "infinite-VCs", i.e. assuming that virtual channels are always available for any flow [6,12,1].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Delay analysis of wormhole based heterogeneous NoC

Ben-Itzhak

Cidon

Kolodny

2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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We introduce a novel evaluation methodology to analyze the delay of a wormhole routing based NoC with variable link capacities and a variable number of virtual channels per link. This methodology can be utilized to analyze different heterogeneous NoC architectures and traffic scenarios for which no analysis framework has been developed before. In particular, it can replace computationally-extensive simulations at the inner-loop of the link capacities and virtual channels allocation steps of the NoC topology optimization process. Our analysis introduces a set of implicit equations which can be efficiently solved iteratively. We demonstrate the accuracy of our approximation by comparing the analysis results to a simulation model for several use-cases and synthetic examples. In addition, we compare the analysis with simulation results for a chip-multi-processor (CMP) using SPLASH-2 and PARSEC traces for both homogeneous and heterogeneous NoC configurations.

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An analytical method for evaluating Network-on-Chip performance

Cited by 26 publications

References 11 publications

Model of Network-on-Chip routers and performance analysis

Model of Network-on-Chip routers and performance analysis

A Buffer‐Sizing Algorithm for Network‐on‐Chips with Multiple Voltage‐Frequency Islands

Delay analysis of wormhole based heterogeneous NoC

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