A Buffer‐Sizing Algorithm for Network‐on‐Chips with Multiple Voltage‐Frequency Islands

Kumar, Anish; Kumar, Mayank; Murali, Srinivasan; Kamakoti, V.; Benini, Luca; Micheli, Giovanni De

doi:10.1155/2012/537286

Cited by 6 publications

(3 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The latency of a link is the addition of the latency to traverse the Frequency Boosting Mechanism (FBM) in the router and link latency. The latency of the link is defined by the frequency at which the link is operated [36]. Let router_distance denote the distance in mm a signal can traverse in 1 .…”

Section: Latencymentioning

confidence: 99%

See 1 more Smart Citation

FSM Based DFS Link for Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

et al. 2016

View full text Add to dashboard Cite

As low power consumption is the main design issue involved in a network on chip (NoC), researchers are concentrating more on both algorithms and architectural approaches. The conventional Dynamic Frequency Scaling (DFS) and history based Frequency Scaling (HDFS) algorithms are utilized to process the energy constrained data traffic. However, these conventional algorithms achieve higher energy efficiencies, and they result in performance degradation due to the auxiliary latency between clock domains. In this paper, we present a variable power optimization interface for NoC using a Finite State Machine (FSM) approach to attain better performance improvement. The parameters are estimated using 45 nm TSMC CMOS technology. In comparison with DFS system, the evaluation results show that FSM-DFS link achieves 81.55% dynamic power savings on the links in the on-chip network, and 37.5% leakage power savings of the link. Also, this proposed work is evaluated for various performance parameters and compared with conventional work. The simulation results are superior to conventional work. Keywords Network-on-Chip (NoC), Dynamic Frequency Scaling (DFS), Finite State Machines (FSM)How to cite this paper: Sakthivel, E., Malathi, V., Arunraja, M. and Perumalvignesh, G. (2016) FSM Based DFS Link for Network on Chip. Circuits and Systems, 7, 1734-1750. http://dx.doi.org/10.4236/cs.2016.78150 E. Sakthivel et al. achieve peak performance of 1.0TFLOPS at 1 V, while dissipating 98 w [3].In [4], the Tile 64 processor design considerations such as arbitration, topology and length of physical links, width of physical links, buffer allocation, switching techniques, routing algorithms, and levels of service are addressed in the NoC core. This architectural challenge through "tiled" architecture can be connected by scalable and energy-efficient architecture.In general, the NoC architecture provides performance degradation by means of more scalability and high power consumption [5]. To achieve lower power consumption and a high operating speed, designers prefer the Dynamic Voltage and Frequency Scaling algorithm (DVFS) [6]. To avoid this complication, History based Dynamic Frequency Scaling (H-DFS) is introduced by Lee et al. [7]. In [8], Dynamic Voltage Scaling algorithm (DVS) implemented in a scalable architecture is developed by external circuit combinations of system configurations. The existing low power algorithms are used to reduce power consumption by adjusting the power mode of the links to match the traffic flows. These algorithms fail to act on sudden traffic changes. To overcome this issue, a novel application-driven approach for predicting traffic described in [9]. Here, a novel data structure called Application Traffic Prediction Table (ATPT) is used to record the core's outgoing messages (traffic) and the DFS policy is applied to the link. Conventional traffic generation is a novel structural design template that yields a complicated system level design [9]. In modern research, reducing the data access latency and energy consum...

show abstract

Section: Latencymentioning

confidence: 99%

“…The bandwidth of a link is given by the product of the link width and frequency of operation of the link [36];…”

Section: Bandwidthmentioning

confidence: 99%

FSM Based DFS Link for Network on Chip

Sakthivel¹,

Veeraraghavan²,

Arunraja³

et al. 2016

View full text Add to dashboard Cite

show abstract

“…To enhance the performance of various applications in NoCs by efficiently redistributing the buffer spaces, it is crucial to accurately model congestion and hotspot regions in different applications. Kumar et al [48] proposed a buffer-sizing algorithm for application-specific NoCs with multiple voltage-frequency islands. Here, the buffers are increased iteratively based on the NoC's behaviour under simulation.…”

Section: Design Automation In Heterogeneous 3d Nocsmentioning

confidence: 99%

A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications

Agyeman¹

2015

IJCA

View full text Add to dashboard Cite

Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest to solve on-chip communication demands of future multi-core embedded systems. However, 3D NoCs have not been completely accepted into the mainstream due to issues such as the high cost and complexity of manufacturing 3D vertical wires, larger memory, area and power consumption of 3D NoC components than that of conventional 2D NoC. This paper presents a brief about 3D NoCs optimization techniques with focus on modeling and evaluation of alternate NoC topologies, routing algorithms and mapping techniques to achieve optimized area, power and performance parameters (latency and throughput). Particularly, we investigate novel 3D NoC router architectures and their possible combinations which aim at achieving lower area and power consumption of on-chip communication components with a minimal performance trade-off.

show abstract