An Analytical Integration Method for the Simulation of Continuous-Time&amp;lt;tex&amp;gt;$DeltaSigma$&amp;lt;/tex&amp;gt;Modulators

Gielen, Georges; Francken, K.; Martens, Ewout; Vogels, M.

doi:10.1109/tcad.2004.823356

Cited by 27 publications

(11 citation statements)

References 9 publications

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“…To solve this also numerically as proposed in (5), the first integral has to be modified. This is done by factor out the constant term e A:ðTÀELDÞ resulting in…”

Section: Excess Loop Delaymentioning

confidence: 99%

“…Thus, they have to be solved numerically by a fancy implicit or explicit iterative method. To keep the resulting error below a specified tolerance level, the simulation step size has to be adjusted accordingly and is therefore generally much smaller than the sample time of the modulator, which enormously increases the simulation time [5]. On the other hand, DT simulations performed on DT modulators do not only offer tremendous speed advantages, but their results are also accurate within the computer's precision.…”

Section: Introductionmentioning

confidence: 99%

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DISCO: a graphical methodology for the design of Sigma-Delta modulators

Buhmann

Keller

Maurer

et al. 2008

Analog Integr Circ Sig Process

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A MATLAB TM toolbox for the design and simulation of continuous time (CT) and discrete time Sigma-Delta modulators is presented. The design of Sigma-Delta modulators is performed by placing the poles and zeros of the loop filter and estimating the resulting noise transfer function and signal transfer function. For this, the toolbox offers a graphical user interface for direct user interaction. Several additional functions, e.g. excess loop delay compensation, are made available to the designer. Further, the designed loop filter can be synthesized in CIFF and CIFB topology or CRFF and CRFB in the case of a bandpass modulator. Additionally, the toolbox offers the design of a closed loop Sigma-Delta sensor readout having the sensor as part of the loop filter. Furthermore, several typical non-idealities of CT Sigma-Delta modulators such as real opamp behavior, excess loop delay, and jitter, are simulated with a tremendously speed up via the application of the lifting approach.

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“…To solve this also numerically as proposed in (5), the first integral has to be modified. This is done by factor out the constant term e A:ðTÀELDÞ resulting in…”

Section: Excess Loop Delaymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

DISCO: a graphical methodology for the design of Sigma-Delta modulators

Buhmann

Keller

Maurer

et al. 2008

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…Reference [2,3] proposed methods for the discrete-time (DT) state-space (SS) simulation of CTDSM. Using a DT state-space matrix enhances simulation speed and eliminates the need for user control of the simulation time-step and solver tolerance, allowing precise results to be achieved more rapidly.…”

Section: Introductionmentioning

confidence: 99%

Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

Na¹,

Kim²,

Yang³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuitlevel simulation using Verilog-A blocks are used to validate our approach.

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“…Continuous-time modulators consume low power and operates at high sampling rate. Many publications have presented non-idealities modeling either in the discrete-time case [1] [2] [3] [4] or the continuous-time one [5] [6] [7]. They model poles/zeros limitations, clock jitter, noise, saturation, harmonic distortion, other non-linearities.…”

Section: Introductionmentioning

confidence: 99%

Automatic model refinement of GmC integrators for high-level simulation of continuous-time Sigma-Delta modulators

Vasilevski

Aboushady

Louërat

2009

2009 IEEE International Symposium on Circuits and Systems

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Abstract-A Σ∆ GmC integrator refinement flow is presented. The classically simplified GmC integrator small-signal model was upgraded to be extremely accurate by considering the complete transistor small-signal model. A circuit-level knowledge-based tool was used to execute the designer defined sizing procedure and to extract small signal parameters. By associating the symbolic transfer function to small-signal parameters, the flow, entirely implemented with C++, is able to compute poles and zeros to permit precise behavioral simulations. A 2 nd order Σ∆ modulator was chosen to visualize performance degradations while the specifications were not achievable. I. INTRODUCTIONThe essential target of simulation is evaluation of performances. When measuring non-linear devices such as Σ∆ modulators, a time-domain analysis is required. Performances are extracted through spectral analysis, requiring a sufficient number of simulation samples to be accurate enough. Running those simulations at transistor-level is time consuming. Designers have to deal with levels of abstraction to handle the trade-off between simulation speed and accuracy of results. That's why a great challenge is to refine behavioral models with a large amount of non-idealities.Σ∆ modulators are well known for their performances. They are used in high resolution audio and wireless applications. Continuous-time modulators consume low power and operates at high sampling rate. Many publications have presented non-idealities modeling either in the discrete-time case [7]. They model poles/zeros limitations, clock jitter, noise, saturation, harmonic distortion, other non-linearities. Characterization of these non-idealities is still often based on circuit-level simulation. Expressing non-idealities as function of circuit small signal parameters is always valuable since it permits automatic model refinement and architecture exploration [8].Focusing on poles/zeros characterization, symbolic analysis [2] [9] has proved its worth to refine behavioral transfer function. This way, technology independent functions can describe a circuit. By choosing a technology, small-signal parameters of the circuit allow to finally determine the values of poles and zeros. Such extraction is generally simulationbased [9]. There are many variants, for example, [7] introduced curve fitting also based on simulation.In this paper, we investigated continuous-time Σ∆ GmC integrators. First, we present a precise small-signal model of a GmC integrator. Then, a circuit-level knowledge-based

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An Analytical Integration Method for the Simulation of Continuous-Time<tex>$DeltaSigma$</tex>Modulators

Cited by 27 publications

References 9 publications

DISCO: a graphical methodology for the design of Sigma-Delta modulators

DISCO: a graphical methodology for the design of Sigma-Delta modulators

Estimating Non-Ideal Effects within a Top-Down Methodology for the Design of Continuous-Time Delta-Sigma Modulators

Automatic model refinement of GmC integrators for high-level simulation of continuous-time Sigma-Delta modulators

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