An analytical framework for first-order CMOS device design

Abstract

We have constructed a simple physics-based analytical framework for MOSFET device simulation. The suite of models is optimized for "well designed" devices that exhibit sufficient electrostatic integrity. This is assessed by means of an analytical model for drain-induced barrier lowering. Using the developed framework, we have simulated 0.1 #m n-channel MOSFETs fabricated at MIT. The agreement obtained between simulations and experiments suggests the viability of this approach in the sub-0.1 #m regime. This analytical framework could form the basis of a compact and efficient first-order CMOS device design environment that could be used to explore key trade-offs and constraints involved in device design several generations ahead. Such a framework could find applications in roadmap planning, sensitivity analysis, and microelectronics education.